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[Qemu-devel] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helper
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers |
Date: |
Thu, 11 May 2017 14:14:05 +1000 |
From: Nikunj A Dadhania <address@hidden>
Emulating LL/SC with cmpxchg is not correct, since it can suffer from
the ABA problem. However, portable parallel code is written assuming
only cmpxchg which means that in practice this is a viable alternative.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f40b5a1..50b6d4d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -73,6 +73,7 @@ static TCGv cpu_cfar;
#endif
static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
static TCGv cpu_reserve;
+static TCGv cpu_reserve_val;
static TCGv cpu_fpscr;
static TCGv_i32 cpu_access_type;
@@ -181,6 +182,9 @@ void ppc_translate_init(void)
cpu_reserve = tcg_global_mem_new(cpu_env,
offsetof(CPUPPCState, reserve_addr),
"reserve_addr");
+ cpu_reserve_val = tcg_global_mem_new(cpu_env,
+ offsetof(CPUPPCState, reserve_val),
+ "reserve_val");
cpu_fpscr = tcg_global_mem_new(cpu_env,
offsetof(CPUPPCState, fpscr), "fpscr");
@@ -3023,7 +3027,7 @@ static void gen_##name(DisasContext *ctx)
\
} \
tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
tcg_gen_mov_tl(cpu_reserve, t0); \
- tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
+ tcg_gen_mov_tl(cpu_reserve_val, gpr); \
tcg_temp_free(t0); \
}
@@ -3155,14 +3159,27 @@ static void gen_conditional_store(DisasContext *ctx,
TCGv EA,
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int memop)
{
- TCGLabel *l1;
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv t0;
- tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
- l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
- tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
+
+ t0 = tcg_temp_new();
+ tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
+ cpu_gpr[reg], ctx->mem_idx,
+ DEF_MEMOP(memop) | MO_ALIGN);
+ tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
+ tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
+ tcg_gen_or_tl(t0, t0, cpu_so);
+ tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
+ tcg_temp_free(t0);
+ tcg_gen_br(l2);
+
gen_set_label(l1);
+ tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+
+ gen_set_label(l2);
tcg_gen_movi_tl(cpu_reserve, -1);
}
#endif
--
2.9.3
- [Qemu-devel] [PULL 00/23] ppc-for-2.10 queue 20170511, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 03/23] cputlb: handle first atomic write to the page, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers,
David Gibson <=
- [Qemu-devel] [PULL 04/23] target/ppc: Generate fence operations, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 01/23] ppc/pnv: restrict BMC object to the BMC simulator, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 12/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 07/23] target/ppc: do not reset reserve_addr in exec_enter, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 15/23] target/ppc: Update tlbie to check privilege level based on GTSE, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 05/23] cpus: Fix CPU unplug for MTTCG, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 08/23] ppc/xics: Fix stale irq->status bits after get, David Gibson, 2017/05/11
- [Qemu-devel] [PULL 13/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs, David Gibson, 2017/05/11