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[Qemu-devel] [PULL 7/9] target/s390x: mask the SIGP order_code using SIG
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 7/9] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK |
Date: |
Fri, 12 May 2017 16:40:07 -0700 |
From: Aurelien Jarno <address@hidden>
For that move the definition from kvm.c to cpu.h
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/s390x/cpu.h | 3 +++
target/s390x/kvm.c | 2 --
target/s390x/misc_helper.c | 3 +--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index bbed320..240b8a5 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -1078,6 +1078,9 @@ struct sysib_322 {
#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
+/* SIGP order code mask corresponding to bit positions 56-63 */
+#define SIGP_ORDER_MASK 0x000000ff
+
void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
target_ulong *raddr, int *flags, bool exc);
diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
index 1a249d8..fb10542 100644
--- a/target/s390x/kvm.c
+++ b/target/s390x/kvm.c
@@ -1764,8 +1764,6 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t
param,
return SIGP_CC_ORDER_CODE_ACCEPTED;
}
-#define SIGP_ORDER_MASK 0x000000ff
-
static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1)
{
CPUS390XState *env = &cpu->env;
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
index bd94242..23ec52c 100644
--- a/target/s390x/misc_helper.c
+++ b/target/s390x/misc_helper.c
@@ -517,8 +517,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t
order_code, uint32_t r1,
/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
as parameter (input). Status (output) is always R1. */
- /* sigp contains the order code in bit positions 56-63, mask it here. */
- switch (order_code & 0xff) {
+ switch (order_code & SIGP_ORDER_MASK) {
case SIGP_SET_ARCH:
/* switch arch */
break;
--
2.9.3
- [Qemu-devel] [PULL 0/9] Queued s390 patches, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 1/9] target/s390x: Implement STORE FACILITIES LIST EXTENDED, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 2/9] target/s390x: Implement LOAD PROGRAM PARAMETER, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 4/9] target/s390x: Implement LOAD PAIR DISJOINT, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 3/9] target/s390x: Diagnose specification exception for atomics, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 5/9] target/s390x: Use atomic operations for COMPARE SWAP, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 6/9] target/s390x: Use atomic operations for LOAD AND OP, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 7/9] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK,
Richard Henderson <=
- [Qemu-devel] [PULL 8/9] target/s390x: fix SIGNAL PROCESSOR return value, Richard Henderson, 2017/05/12
- [Qemu-devel] [PULL 9/9] target/s390x: implement serialization in BRANCH CONDITION, Richard Henderson, 2017/05/12
- Re: [Qemu-devel] [PULL 0/9] Queued s390 patches, Stefan Hajnoczi, 2017/05/15