Re: [Qemu-devel] qemu-system-sh4 -M r2d serial is broken.

[Aurelien Jarno]

On 2017-05-18 21:57, Paolo Bonzini wrote:
> Anyway, Uli Hecht is saying SCIF "asserts DR even if the FIFO threshold
> has not been reached if no data is received for 1.5 frames".  If that's
> just a register and doesn't trigger an interrupt, you can compute the
> bit's value dynamically based on the current clock.
> 
> This is for example how the x86 RTC chip computes the "update in
> progress" bit, which is set for 220 us before the RC updates.  Doing
> that with a timer would be really imprecise.

Unfortunately, the DR bit is set to 1 after 1.5 frames (so the exact
timing depends on the actual baud rate), and that also triggers an
interrupt if the RIE bit is set to 1. I haven't checked yet if the
kernel relies on the bit or the interrupt or both.

Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
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