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[Qemu-devel] [PULL 07/33] msix: trace control bit write op
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 07/33] msix: trace control bit write op |
Date: |
Thu, 1 Jun 2017 14:41:25 +0200 |
From: Peter Xu <address@hidden>
Meanwhile, abstract a function to detect msix masked bit.
Signed-off-by: Peter Xu <address@hidden>
Message-Id: <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
hw/pci/msix.c | 11 +++++++++--
hw/pci/trace-events | 3 +++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index bb54e8b..fc5fe51 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -22,6 +22,7 @@
#include "hw/xen/xen.h"
#include "qemu/range.h"
#include "qapi/error.h"
+#include "trace.h"
#define MSIX_CAP_LENGTH 12
@@ -130,10 +131,14 @@ static void msix_handle_mask_update(PCIDevice *dev, int
vector, bool was_masked)
}
}
+static bool msix_masked(PCIDevice *dev)
+{
+ return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
MSIX_MASKALL_MASK;
+}
+
static void msix_update_function_masked(PCIDevice *dev)
{
- dev->msix_function_masked = !msix_enabled(dev) ||
- (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
+ dev->msix_function_masked = !msix_enabled(dev) || msix_masked(dev);
}
/* Handle MSI-X capability config write. */
@@ -148,6 +153,8 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
return;
}
+ trace_msix_write_config(dev->name, msix_enabled(dev), msix_masked(dev));
+
was_masked = dev->msix_function_masked;
msix_update_function_masked(dev);
diff --git a/hw/pci/trace-events b/hw/pci/trace-events
index 2b9cf24..83c8f5a 100644
--- a/hw/pci/trace-events
+++ b/hw/pci/trace-events
@@ -7,3 +7,6 @@ pci_update_mappings_add(void *d, uint32_t bus, uint32_t slot,
uint32_t func, int
# hw/pci/pci_host.c
pci_cfg_read(const char *dev, unsigned devid, unsigned fnid, unsigned offs,
unsigned val) "%s %02u:%u @0x%x -> 0x%x"
pci_cfg_write(const char *dev, unsigned devid, unsigned fnid, unsigned offs,
unsigned val) "%s %02u:%u @0x%x <- 0x%x"
+
+# hw/pci/msix.c
+msix_write_config(char *name, bool enabled, bool masked) "dev %s enabled %d
masked %d"
--
1.8.3.1
- [Qemu-devel] [PULL 00/33] Misc patches for 2017-06-01, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 01/33] mc146818rtc: update periodic timer only if it is needed, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 04/33] mc146818rtc: drop unnecessary '#ifdef TARGET_I386', Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 07/33] msix: trace control bit write op,
Paolo Bonzini <=
- [Qemu-devel] [PULL 03/33] mc146818rtc: ensure LOST_TICK_POLICY_SLEW is only enabled on TARGET_I386, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 02/33] mc146818rtc: precisely count the clock for periodic timer, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 08/33] kvm: irqchip: skip update msi when disabled, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 09/33] Check the return value of fcntl in qemu_set_cloexec, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 05/33] mc146818rtc: embrace all x86 specific code, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 10/33] nbd: strict nbd_wr_syncv, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 06/33] kvm: irqchip: trace changes on msi add/remove, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 15/33] exec: simplify phys_page_find() params, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 14/33] nbd/client.c: use errp instead of LOG, Paolo Bonzini, 2017/06/01
- [Qemu-devel] [PULL 12/33] nbd: add errp parameter to nbd_wr_syncv(), Paolo Bonzini, 2017/06/01