Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction

[Thomas Huth]

On 14.06.2017 09:56, David Hildenbrand wrote:
[...]
>> I think you should also mask the length with 0xffffffff if the PSW was
>> not in 64-bit mode? Or is this done automagically by the generated TCG
>> code already?
> 
> I was asking myself the same question, but it shouldn't really matter as
> was we will be using a maximum of 4096, no?

Question is whether we can end up here somehow in 32-bit mode and the
upper part of the register is still != 0 ... something like 0x100000010
for example. Can we be sure that the upper half is always cleared if we
switch from 64-bit mode to the 32-bit mode before?

 Thomas