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[Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs
From: |
Peter Maydell |
Subject: |
[Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs |
Date: |
Fri, 16 Jun 2017 18:34:02 +0100 |
Hi; I just noticed that we seem to still implement the ARM v6
memory-barrier cp15 ops as NOPs:
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
.access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
{ .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
.access = PL0_W, .type = ARM_CP_NOP },
{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
.access = PL0_W, .type = ARM_CP_NOP },
Don't these need to do something more complicated with the
advent of MTTCG ?
thanks
-- PMM
- [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs,
Peter Maydell <=