Re: [Qemu-devel] [PATCH v3] target-ppc: Enable open-pic timers to count and generate interrupts

[alarson]

G 3 <address@hidden> wrote on 06/18/2017 03:38:29 PM:
> >>>>> From: Aaron Larson <address@hidden>
> >>>>> Date: 06/05/2017 12:22 PM
> >>>>> Subject: [PATCH v3] target-ppc: Enable open-pic timers to count 
> >>>>> and generate interrupts
> >>>>>
> >>>>> Previously QEMU open-pic implemented the 4 open-pic timers
> >>>>> including all timer registers, but the timers did not "count"
> >>>>> or generate any interrupts.  The patch makes the timers both
> >>>>> count and generate interrupts.  The timer clock frequency is
> >>>>> fixed at 25MHZ.
> >
> > G3> Does QEMU behave differently after this patch is implemented?
> >
> > If the open-pic timers are programmed, then QEMU behaves
> > differently, otherwise there should be no difference.
> 
> I guess I should have asked what differences did you see in QEMU's 
> behavior?

In the past, the open-pic timers were, effectively, unimplemented.
They allowed a write to the timer registers, e.g., to enable a
counter, but the counter never "counted", instead just returning
whatever was most recently programmed.

Now the timers are, well, timers.  Given the previous implementation,
it was highly unlikely any software running on QEMU actually used the
timers, so in general I would expect there would be no difference at
all.