Re: [Qemu-devel] [PATCH v1 5/8] target-microblaze: Introduce a use-div property

[Alistair Francis]

On Tue, Jun 20, 2017 at 8:51 AM, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Introduce a use-div property making division instructions
> optional.
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Thanks,
Alistair

> ---
>  target/microblaze/cpu.c       | 9 +++++----
>  target/microblaze/cpu.h       | 1 +
>  target/microblaze/translate.c | 2 +-
>  3 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index bae47b5..5bf2a29 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
> **errp)
>
>      qemu_init_vcpu(cs);
>
> -    env->pvr.regs[0] = PVR0_USE_DIV_MASK \
> -                       | PVR0_USE_HW_MUL_MASK \
> +    env->pvr.regs[0] = PVR0_USE_HW_MUL_MASK \
>                         | PVR0_USE_EXC_MASK \
>                         | PVR0_USE_ICACHE_MASK \
>                         | PVR0_USE_DCACHE_MASK;
> @@ -161,7 +160,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
> **errp)
>                          | PVR2_I_LMB_MASK \
>                          | PVR2_USE_MSR_INSTR \
>                          | PVR2_USE_PCMP_INSTR \
> -                        | PVR2_USE_DIV_MASK \
>                          | PVR2_USE_HW_MUL_MASK \
>                          | PVR2_USE_MUL64_MASK \
>                          | PVR2_FPU_EXC_MASK \
> @@ -181,6 +179,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
> **errp)
>      env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
>                          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
> +                        (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
>                          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
>                          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
>                          (version_code << PVR0_VERSION_SHIFT) |
> @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
> **errp)
>
>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
> -                        (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0);
> +                        (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
> +                        (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0);
>
>      env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
>                                          PVR5_DCACHE_WRITEBACK_MASK : 0;
> @@ -236,6 +236,7 @@ static Property mb_properties[] = {
>       */
>      DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
>      DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
> +    DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
>      DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
>      DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
>                       false),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 2a4a65a..4397338 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -299,6 +299,7 @@ struct MicroBlazeCPU {
>          uint32_t base_vectors;
>          uint8_t use_fpu;
>          bool use_barrel;
> +        bool use_div;
>          bool use_mmu;
>          bool dcache_writeback;
>          bool endi;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 26b221c..afe4bd4 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -643,7 +643,7 @@ static void dec_div(DisasContext *dc)
>      LOG_DIS("div\n");
>
>      if ((dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
> -          && !((dc->cpu->env.pvr.regs[0] & PVR0_USE_DIV_MASK))) {
> +          && !dc->cpu->cfg.use_div) {
>          tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
>          t_gen_raise_exception(dc, EXCP_HW_EXCP);
>      }
> --
> 2.7.4
>
>