Re: [Qemu-devel] [PATCH v3 07/18] target/s390x: Implement load-and-zero-rightmost-byte insns

[Aurelien Jarno]

On 2017-06-19 17:03, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/s390x/insn-data.def | 4 ++++
>  target/s390x/translate.c   | 7 +++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index 60d244f..20dec56 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -429,6 +429,10 @@
>  /* LOAD AND TRAP */
>      C(0xe39f, LAT,     RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0)
>      C(0xe385, LGAT,    RXY_a, LAT, 0, a2, r1, 0, lgat, 0)
> +/* LOAD AND ZERO RIGHTMOST BYTE */
> +    C(0xe3eb, LZRF,    RXY_a, LZRB, 0, m2_32u, new, r1_32, lzrb, 0)
> +    C(0xe32a, LZRG,    RXY_a, LZRB, 0, m2_64, r1, 0, lzrb, 0)
> +    C(0xe33a, LLZRGF,  RXY_a, LZRB, 0, m2_32u, r1, 0, lzrb, 0)

Small nitpick, LLZRGF is considered a separate instruction in the PoO,
called LOAD LOGICAL AND ZERO RIGHTMOST BYTE.

That said:

Reviewed-by: Aurelien Jarno <address@hidden>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net