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[Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH |
Date: |
Fri, 23 Jun 2017 09:22:37 -0700 |
Missed the proper alignment in TRTO/TRTT, and ignoring the M3
field for all TRXX insns without ETF2-ENH.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/s390x/mem_helper.c | 11 ++++++++++-
target/s390x/translate.c | 5 +++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 6125725..a0a805c 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1265,13 +1265,22 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1,
uint32_t r2,
uintptr_t ra = GETPC();
int dsize = (sizes & 1) ? 1 : 2;
int ssize = (sizes & 2) ? 1 : 2;
- uint64_t tbl = get_address(env, 1) & ~7;
+ uint64_t tbl = get_address(env, 1);
uint64_t dst = get_address(env, r1);
uint64_t len = get_length(env, r1 + 1);
uint64_t src = get_address(env, r2);
uint32_t cc = 3;
int i;
+ /* The lower address bits of TBL are ignored. For TROO, TROT, it's
+ the low 3 bits (double-word aligned). For TRTO, TRTT, it's either
+ the low 12 bits (4K, without ETF2-ENH) or 3 bits (with ETF2-ENH). */
+ if (ssize == 2 && !s390_has_feat(S390_FEAT_ETF2_ENH)) {
+ tbl &= -4096;
+ } else {
+ tbl &= -8;
+ }
+
check_alignment(env, len, ssize, ra);
/* Lest we fail to service interrupts in a timely manner, */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 72af76d..a3414c0 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4356,8 +4356,9 @@ static ExitStatus op_trXX(DisasContext *s, DisasOps *o)
TCGv_i32 tst = tcg_temp_new_i32();
int m3 = get_field(s->fields, m3);
- /* XXX: the C bit in M3 should be considered as 0 when the
- ETF2-enhancement facility is not installed. */
+ if (!s390_has_feat(S390_FEAT_ETF2_ENH)) {
+ m3 = 0;
+ }
if (m3 & 1) {
tcg_gen_movi_i32(tst, -1);
} else {
--
2.9.4
- [Qemu-devel] [PULL 00/15] Queued target/s390x patches, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 01/15] target/s390x: Map existing FAC_* names to S390_FEAT_* names, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 02/15] target/s390x: change PSW_SHIFT_KEY, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 05/15] target/s390x: Implement load-on-condition-2 insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 03/15] target/s390x: implement mvcos instruction, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 07/15] target/s390x: Mark STFLE_53 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 09/15] target/s390x: Implement processor-assist insn, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 10/15] target/s390x: Mark STFLE_49 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH,
Richard Henderson <=
- [Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 13/15] target/s390x: Indicate and check for local tlb clearing, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction, Richard Henderson, 2017/06/23
- Re: [Qemu-devel] [PULL 00/15] Queued target/s390x patches, Peter Maydell, 2017/06/26