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[Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction |
Date: |
Fri, 23 Jun 2017 09:22:41 -0700 |
From: David Hildenbrand <address@hidden>
Let's keep it very simple for now and flush the complete tlb,
we currently can't find the right entries in our tlb, we would have
to store the used tables for each element.
As we now fully implement the DAT-enhancement facility, we can allow to
enable it for the qemu CPU model.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/s390x/cpu_models.c | 1 +
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
target/s390x/translate.c | 15 ++++++++++++++
5 files changed, 70 insertions(+)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 51b17b9..63903c2 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -675,6 +675,7 @@ static void check_compatibility(const S390CPUModel
*max_model,
static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
{
static const int feats[] = {
+ S390_FEAT_DAT_ENH,
S390_FEAT_STFLE,
S390_FEAT_EXTENDED_IMMEDIATE,
S390_FEAT_EXTENDED_TRANSLATION_2,
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index b268367..964097b 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -131,6 +131,7 @@ DEF_HELPER_4(mvcs, i32, env, i64, i64, i64)
DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)
DEF_HELPER_4(sigp, i32, env, i64, i32, i64)
DEF_HELPER_FLAGS_2(sacf, TCG_CALL_NO_WG, void, env, i64)
+DEF_HELPER_FLAGS_4(idte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)
DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)
DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 5ba7822..d3bb851 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -928,6 +928,8 @@
C(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0)
/* INSERT STORAGE KEY EXTENDED */
C(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0)
+/* INVALIDATE DAT TABLE ENTRY */
+ C(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0)
/* INVALIDATE PAGE TABLE ENTRY */
C(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0)
/* LOAD CONTROL */
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 20cef9a..ede8471 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1610,6 +1610,57 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l,
uint64_t a1, uint64_t a2)
return cc;
}
+void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
+{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
+ const uintptr_t ra = GETPC();
+ uint64_t table, entry, raddr;
+ uint16_t entries, i, index = 0;
+
+ if (r2 & 0xff000) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIFICATION, 4);
+ }
+
+ if (!(r2 & 0x800)) {
+ /* invalidation-and-clearing operation */
+ table = r1 & _ASCE_ORIGIN;
+ entries = (r2 & 0x7ff) + 1;
+
+ switch (r1 & _ASCE_TYPE_MASK) {
+ case _ASCE_TYPE_REGION1:
+ index = (r2 >> 53) & 0x7ff;
+ break;
+ case _ASCE_TYPE_REGION2:
+ index = (r2 >> 42) & 0x7ff;
+ break;
+ case _ASCE_TYPE_REGION3:
+ index = (r2 >> 31) & 0x7ff;
+ break;
+ case _ASCE_TYPE_SEGMENT:
+ index = (r2 >> 20) & 0x7ff;
+ break;
+ }
+ for (i = 0; i < entries; i++) {
+ /* addresses are not wrapped in 24/31bit mode but table index is */
+ raddr = table + ((index + i) & 0x7ff) * sizeof(entry);
+ entry = ldq_phys(cs->as, raddr);
+ if (!(entry & _REGION_ENTRY_INV)) {
+ /* we are allowed to not store if already invalid */
+ entry |= _REGION_ENTRY_INV;
+ stq_phys(cs->as, raddr, entry);
+ }
+ }
+ }
+
+ /* We simply flush the complete tlb, therefore we can ignore r3. */
+ if (m4 & 1) {
+ tlb_flush(cs);
+ } else {
+ tlb_flush_all_cpus_synced(cs);
+ }
+}
+
/* invalidate pte */
void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
uint32_t m4)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 1db5f2d..592d6b0 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2380,6 +2380,21 @@ static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
}
#ifndef CONFIG_USER_ONLY
+static ExitStatus op_idte(DisasContext *s, DisasOps *o)
+{
+ TCGv_i32 m4;
+
+ check_privileged(s);
+ if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
+ m4 = tcg_const_i32(get_field(s->fields, m4));
+ } else {
+ m4 = tcg_const_i32(0);
+ }
+ gen_helper_idte(cpu_env, o->in1, o->in2, m4);
+ tcg_temp_free_i32(m4);
+ return NO_EXIT;
+}
+
static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
--
2.9.4
- [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available, (continued)
- [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 03/15] target/s390x: implement mvcos instruction, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 07/15] target/s390x: Mark STFLE_53 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 09/15] target/s390x: Implement processor-assist insn, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 10/15] target/s390x: Mark STFLE_49 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 13/15] target/s390x: Indicate and check for local tlb clearing, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction,
Richard Henderson <=
- Re: [Qemu-devel] [PULL 00/15] Queued target/s390x patches, Peter Maydell, 2017/06/26