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[Qemu-devel] [Intel-gfx][RFC 2/9] drm/i915/gvt: Apply g2h adjustment dur
From: |
Yulei Zhang |
Subject: |
[Qemu-devel] [Intel-gfx][RFC 2/9] drm/i915/gvt: Apply g2h adjustment during fence mmio access |
Date: |
Mon, 26 Jun 2017 08:59:12 -0000 |
Apply the guest to host gma conversion while guest config the
fence mmio registers due to the host gma change after the migration.
Signed-off-by: Yulei Zhang <address@hidden>
---
drivers/gpu/drm/i915/gvt/aperture_gm.c | 6 ++++--
drivers/gpu/drm/i915/gvt/gvt.h | 14 ++++++++++++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c
b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index ca3d192..cd68ec6 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -144,8 +144,10 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
I915_WRITE(fence_reg_lo, 0);
POSTING_READ(fence_reg_lo);
- I915_WRITE(fence_reg_hi, upper_32_bits(value));
- I915_WRITE(fence_reg_lo, lower_32_bits(value));
+ I915_WRITE(fence_reg_hi,
+ intel_gvt_reg_g2h(vgpu, upper_32_bits(value),
0xFFFFF000));
+ I915_WRITE(fence_reg_lo,
+ intel_gvt_reg_g2h(vgpu, lower_32_bits(value),
0xFFFFF000));
POSTING_READ(fence_reg_lo);
}
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 3a74e79..71c00b2 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -451,6 +451,20 @@ int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu,
unsigned long g_index,
int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
unsigned long *g_index);
+/* apply guest to host gma convertion in GM registers setting */
+static inline u64 intel_gvt_reg_g2h(struct intel_vgpu *vgpu,
+ u32 addr, u32 mask)
+{
+ u64 gma;
+
+ if (addr) {
+ intel_gvt_ggtt_gmadr_g2h(vgpu,
+ addr & mask, &gma);
+ addr = gma | (addr & (~mask));
+ }
+ return addr;
+}
+
void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
bool primary);
void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
--
2.7.4
- [Qemu-devel] [Intel-gfx][RFC 0/9] drm/i915/gvt: Add the live migration support to VFIO mdev deivce - Intel vGPU, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 2/9] drm/i915/gvt: Apply g2h adjustment during fence mmio access,
Yulei Zhang <=
- [Qemu-devel] [Intel-gfx][RFC 6/9] drm/i915/gvt: Introduce new flag to indicate migration capability, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 3/9] drm/i915/gvt: Adjust the gma parameter in gpu commands during command parser, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 8/9] drm/i915/gvt: Introduce new VFIO ioctl for mdev device dirty page sync, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 7/9] drm/i915/gvt: Introduce new VFIO ioctl for device status control, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 4/9] drm/i915/gvt: Retrieve the guest gm base address from PVINFO, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 1/9] drm/i915/gvt: Apply g2h adjust for GTT mmio access, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 5/9] drm/i915/gvt: Align the guest gm aperture start offset for live migration, Yulei Zhang, 2017/06/26
- [Qemu-devel] [Intel-gfx][RFC 9/9] drm/i915/gvt: Add support to VFIO region VFIO_PCI_DEVICE_STATE_REGION_INDEX, Yulei Zhang, 2017/06/26