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[Qemu-devel] [PATCH v11 16/29] target/arm: [tcg, a64] Port to init_disas
From: |
Lluís Vilanova |
Subject: |
[Qemu-devel] [PATCH v11 16/29] target/arm: [tcg, a64] Port to init_disas_context |
Date: |
Wed, 28 Jun 2017 16:21:12 +0300 |
User-agent: |
StGit/0.17.1-dirty |
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <address@hidden>
---
target/arm/translate-a64.c | 36 ++++++++++++++++++++++--------------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 4270ac3847..88624a726d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11190,21 +11190,12 @@ static void disas_a64_insn(CPUARMState *env,
DisasContext *s)
free_tmp_a64(s);
}
-void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
- TranslationBlock *tb)
+static void aarch64_trblock_init_disas_context(DisasContextBase *dcbase,
+ CPUState *cpu)
{
- CPUARMState *env = cs->env_ptr;
- ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext *dc = container_of(dcbase, DisasContext, base);
- target_ulong next_page_start;
- int max_insns;
-
- dc->base.tb = tb;
- dc->base.pc_first = dc->base.tb->pc;
- dc->base.pc_next = dc->base.pc_first;
- dc->base.is_jmp = DISAS_NEXT;
- dc->base.num_insns = 0;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
+ CPUARMState *env = cpu->env_ptr;
+ ARMCPU *arm_cpu = arm_env_get_cpu(env);
dc->pc = dc->base.pc_first;
dc->condjmp = 0;
@@ -11230,7 +11221,7 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
dc->vec_len = 0;
dc->vec_stride = 0;
- dc->cp_regs = cpu->cp_regs;
+ dc->cp_regs = arm_cpu->cp_regs;
dc->features = env->features;
/* Single step state. The code-generation logic here is:
@@ -11254,6 +11245,23 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
init_tmp_a64_array(dc);
+}
+
+void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
+ TranslationBlock *tb)
+{
+ CPUARMState *env = cs->env_ptr;
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ target_ulong next_page_start;
+ int max_insns;
+
+ dc->base.tb = tb;
+ dc->base.pc_first = dc->base.tb->pc;
+ dc->base.pc_next = dc->base.pc_first;
+ dc->base.is_jmp = DISAS_NEXT;
+ dc->base.num_insns = 0;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
+ aarch64_trblock_init_disas_context(&dc->base, cs);
next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) +
TARGET_PAGE_SIZE;
max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
- [Qemu-devel] [PATCH v11 06/29] target/i386: [tcg] Refactor init_disas_context, (continued)
- [Qemu-devel] [PATCH v11 06/29] target/i386: [tcg] Refactor init_disas_context, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 07/29] target/i386: [tcg] Refactor init_globals, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 08/29] target/i386: [tcg] Refactor insn_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 09/29] target/i386: [tcg] Refactor breakpoint_check, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 10/29] target/i386: [tcg] Refactor translate_insn, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 11/29] target/i386: [tcg] Refactor tb_stop, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 12/29] target/i386: [tcg] Refactor disas_log, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 13/29] target/i386: [tcg] Port to generic translation framework, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 14/29] target/arm: [tcg] Port to DisasContextBase, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 15/29] target/arm: [tcg] Port to init_disas_context, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 16/29] target/arm: [tcg, a64] Port to init_disas_context,
Lluís Vilanova <=
- [Qemu-devel] [PATCH v11 17/29] target/arm: [tcg] Port to init_globals, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 18/29] target/arm: [tcg] Port to tb_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 19/29] target/arm: [tcg] Port to insn_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 20/29] target/arm: [tcg, a64] Port to insn_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 21/29] target/arm: [tcg] Port to breakpoint_check, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 22/29] target/arm: [tcg, a64] Port to breakpoint_check, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 23/29] target/arm: [tcg] Port to translate_insn, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 24/29] target/arm: [tcg, a64] Port to translate_insn, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 25/29] target/arm: [tcg] Port to tb_stop, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 26/29] target/arm: [tcg, a64] Port to tb_stop, Lluís Vilanova, 2017/06/28