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| From: | Richard Henderson |
| Subject: | Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG |
| Date: | Fri, 30 Jun 2017 12:22:01 -0700 |
| User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 |
On 06/29/2017 12:05 AM, Thomas Huth wrote:
However, I'm not sure whether you can simply ignore the clearing-by-ASCE stuff in this case. For example, according to the PoP: "When the clearing-by-ASCE-option bit (bit 52 of gen- eral register R2 is one), the M4 field is ignored." And the idte helper function currently always takes the M4 field into account...
I don't see that quote. I see only Bit 2 of the M 4 field is ignored for the clearing-by-ASCE operation and when EDAT-2 does not apply. We don't actually handle bit 2 at all... r~
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