Re: [Qemu-devel] [PATCH v2 05/27] target/sh4: Adjust TB_FLAG_PENDING_MOVCA

[Philippe Mathieu-Daudé]

On 07/06/2017 11:20 PM, Richard Henderson wrote:
> Don't leave an unused bit after DELAY_SLOT_MASK.
>
> Signed-off-by: Richard Henderson <address@hidden>

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>

> ---
>   target/sh4/cpu.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index 6d179a7..da31805 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -96,6 +96,8 @@
>   #define DELAY_SLOT_CONDITIONAL (1 << 1)
>   #define DELAY_SLOT_RTE         (1 << 2)
>   
> +#define TB_FLAG_PENDING_MOVCA  (1 << 3)
> +
>   #define TB_FLAG_ENVFLAGS_MASK  DELAY_SLOT_MASK
>   
>   typedef struct tlb_t {
> @@ -369,8 +371,6 @@ static inline int cpu_ptel_pr (uint32_t ptel)
>   #define PTEA_TC        (1 << 3)
>   #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
>   
> -#define TB_FLAG_PENDING_MOVCA  (1 << 4)
> -
>   static inline target_ulong cpu_read_sr(CPUSH4State *env)
>   {
>       return env->sr | (env->sr_m << SR_M) |
> @@ -395,7 +395,7 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, 
> target_ulong *pc,
>               | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 
> */
>               | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 
> */
>               | (env->sr & (1u << SR_FD))                        /* Bit 15 */
> -            | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
> +            | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
>   }
>   
>   #endif /* SH4_CPU_H */