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[Qemu-devel] [PATCH v13 22/26] target/arm: [tcg] Port to tb_stop
From: |
Lluís Vilanova |
Subject: |
[Qemu-devel] [PATCH v13 22/26] target/arm: [tcg] Port to tb_stop |
Date: |
Fri, 14 Jul 2017 12:42:23 +0300 |
User-agent: |
StGit/0.17.1-dirty |
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <address@hidden>
---
target/arm/translate.c | 165 +++++++++++++++++++++++++-----------------------
target/arm/translate.h | 1
2 files changed, 87 insertions(+), 79 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c60be757dc..f221cbee5d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11967,7 +11967,7 @@ static target_ulong
arm_tr_translate_insn(DisasContextBase *dcbase,
assert(dc->base.num_insns == 1);
gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
default_exception_el(dc));
- dc->base.is_jmp = DISAS_SKIP;
+ dc->base.is_jmp = DISAS_NORETURN;
return dc->pc;
}
@@ -12019,87 +12019,17 @@ static target_ulong
arm_tr_translate_insn(DisasContextBase *dcbase,
return dc->pc;
}
-/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
- DisasContext dc1, *dc = &dc1;
- int max_insns;
-
- /* generate intermediate code */
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- /* The A64 decoder has its own top level loop, because it doesn't need
- * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
- */
- if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
- gen_intermediate_code_a64(&dc->base, cs, tb);
+ if (dc->base.is_jmp == DISAS_NORETURN) {
return;
}
- dc->base.tb = tb;
- dc->base.pc_first = dc->base.tb->pc;
- dc->base.pc_next = dc->base.pc_first;
- dc->base.is_jmp = DISAS_NEXT;
- dc->base.num_insns = 0;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
- arm_tr_init_disas_context(&dc->base, cs);
-
- max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
-
- gen_tb_start(tb);
-
- tcg_clear_temp_count();
- arm_tr_tb_start(&dc->base, cs, &max_insns);
-
- do {
- dc->base.num_insns++;
- arm_tr_insn_start(&dc->base, cs);
-
- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
- CPUBreakpoint *bp;
- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
- if (bp->pc == dc->base.pc_next) {
- if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {
- break;
- }
- }
- }
-
- if (dc->base.is_jmp == DISAS_NORETURN) {
- break;
- }
- }
-
- if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
- }
-
- dc->base.pc_next = arm_tr_translate_insn(&dc->base, cs);
-
- if (tcg_check_temp_count()) {
- fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
- dc->pc);
- }
-
- if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||
- dc->base.num_insns >= max_insns)) {
- dc->base.is_jmp = DISAS_TOO_MANY;
- }
- } while (!dc->base.is_jmp);
-
- if (dc->base.is_jmp != DISAS_SKIP) {
- if (tb->cflags & CF_LAST_IO) {
- if (dc->condjmp) {
- /* FIXME: This can theoretically happen with self-modifying
- code. */
- cpu_abort(cs, "IO on conditional branch instruction");
- }
- gen_io_end();
+ if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) {
+ /* FIXME: This can theoretically happen with self-modifying code. */
+ cpu_abort(cpu, "IO on conditional branch instruction");
}
/* At this stage dc->condjmp will only be set when the skipped
@@ -12203,9 +12133,88 @@ void gen_intermediate_code(CPUState *cs,
TranslationBlock *tb)
gen_goto_tb(dc, 1, dc->pc);
}
}
+}
+
+/* generate intermediate code for basic block 'tb'. */
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+{
+ DisasContext dc1, *dc = &dc1;
+ int max_insns;
+
+ /* generate intermediate code */
+
+ /* The A64 decoder has its own top level loop, because it doesn't need
+ * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
+ */
+ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
+ gen_intermediate_code_a64(&dc->base, cs, tb);
+ return;
+ }
+
+ dc->base.tb = tb;
+ dc->base.pc_first = dc->base.tb->pc;
+ dc->base.pc_next = dc->base.pc_first;
+ dc->base.is_jmp = DISAS_NEXT;
+ dc->base.num_insns = 0;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
+ arm_tr_init_disas_context(&dc->base, cs);
+
+
+ max_insns = tb->cflags & CF_COUNT_MASK;
+ if (max_insns == 0) {
+ max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
+
+ gen_tb_start(tb);
+
+ tcg_clear_temp_count();
+ arm_tr_tb_start(&dc->base, cs, &max_insns);
+
+ do {
+ dc->base.num_insns++;
+ arm_tr_insn_start(&dc->base, cs);
+
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ CPUBreakpoint *bp;
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
+ if (bp->pc == dc->base.pc_next) {
+ if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {
+ break;
+ }
+ }
+ }
+
+ if (dc->base.is_jmp == DISAS_NORETURN) {
+ break;
+ }
+ }
+
+ if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
+ gen_io_start();
+ }
+
+ dc->base.pc_next = arm_tr_translate_insn(&dc->base, cs);
+
+ if (tcg_check_temp_count()) {
+ fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
+ dc->pc);
+ }
+
+ if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||
+ dc->base.num_insns >= max_insns)) {
+ dc->base.is_jmp = DISAS_TOO_MANY;
+ }
+ } while (!dc->base.is_jmp);
+
+ arm_tr_tb_stop(&dc->base, cs);
+
+ if (dc->base.tb->cflags & CF_LAST_IO) {
+ gen_io_end();
}
-done_generating:
gen_tb_end(tb, dc->base.num_insns);
#ifdef DEBUG_DISAS
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 83e56dcb08..720cb102e3 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -149,7 +149,6 @@ static void disas_set_insn_syndrome(DisasContext *s,
uint32_t syn)
* as opposed to attempting to use lookup_and_goto_ptr.
*/
#define DISAS_EXIT DISAS_TARGET_11
-#define DISAS_SKIP DISAS_TARGET_12
#ifdef TARGET_AARCH64
void a64_translate_init(void);
- [Qemu-devel] [PATCH v13 17/26] target/arm: [tcg, a64] Port to insn_start, (continued)
[Qemu-devel] [PATCH v13 19/26] target/arm: [tcg, a64] Port to breakpoint_check, Lluís Vilanova, 2017/07/14
[Qemu-devel] [PATCH v13 20/26] target/arm: [tcg] Port to translate_insn, Lluís Vilanova, 2017/07/14
[Qemu-devel] [PATCH v13 21/26] target/arm: [tcg, a64] Port to translate_insn, Lluís Vilanova, 2017/07/14
[Qemu-devel] [PATCH v13 22/26] target/arm: [tcg] Port to tb_stop,
Lluís Vilanova <=
[Qemu-devel] [PATCH v13 23/26] target/arm: [tcg, a64] Port to tb_stop, Lluís Vilanova, 2017/07/14
[Qemu-devel] [PATCH v13 24/26] target/arm: [tcg] Port to disas_log, Lluís Vilanova, 2017/07/14
[Qemu-devel] [PATCH v13 25/26] target/arm: [tcg, a64] Port to disas_log, Lluís Vilanova, 2017/07/14
[Qemu-devel] [PATCH v13 26/26] target/arm: [tcg] Port to generic translation framework, Lluís Vilanova, 2017/07/14
Re: [Qemu-devel] [PATCH v13 00/26] translate: [tcg] Generic translation framework, no-reply, 2017/07/14