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[Qemu-devel] [PULL 12/18] hw/arm/mps2: Add UARTs
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/18] hw/arm/mps2: Add UARTs |
Date: |
Mon, 17 Jul 2017 13:44:48 +0100 |
Add the UARTs to the MPS2 board models.
Unfortunately the details of the wiring of the interrupts through
various OR gates differ between AN511 and AN385 so this can't
be purely a data-driven difference.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
---
hw/arm/mps2.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++++
hw/char/cmsdk-apb-uart.c | 2 +-
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 22b33ff..9c8fa77 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -27,9 +27,12 @@
#include "qemu/error-report.h"
#include "hw/arm/arm.h"
#include "hw/arm/armv7m.h"
+#include "hw/or-irq.h"
#include "hw/boards.h"
#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
#include "hw/misc/unimp.h"
+#include "hw/char/cmsdk-apb-uart.h"
typedef enum MPS2FPGAType {
FPGA_AN385,
@@ -205,6 +208,91 @@ static void mps2_common_init(MachineState *machine)
create_unimplemented_device("Ethernet", 0x40200000, 0x00100000);
create_unimplemented_device("VGA", 0x41000000, 0x0200000);
+ switch (mmc->fpga_type) {
+ case FPGA_AN385:
+ {
+ /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
+ * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
+ */
+ Object *orgate;
+ DeviceState *orgate_dev;
+ int i;
+
+ orgate = object_new(TYPE_OR_IRQ);
+ object_property_set_int(orgate, 6, "num-lines", &error_fatal);
+ object_property_set_bool(orgate, true, "realized", &error_fatal);
+ orgate_dev = DEVICE(orgate);
+ qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
+
+ for (i = 0; i < 5; i++) {
+ static const hwaddr uartbase[] = {0x40004000, 0x40005000,
+ 0x40006000, 0x40007000,
+ 0x40009000};
+ Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
+ /* RX irq number; TX irq is always one greater */
+ static const int uartirq[] = {0, 2, 4, 18, 20};
+ qemu_irq txovrint = NULL, rxovrint = NULL;
+
+ if (i < 3) {
+ txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
+ rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
+ }
+
+ cmsdk_apb_uart_create(uartbase[i],
+ qdev_get_gpio_in(armv7m, uartirq[i] + 1),
+ qdev_get_gpio_in(armv7m, uartirq[i]),
+ txovrint, rxovrint,
+ NULL,
+ uartchr, SYSCLK_FRQ);
+ }
+ break;
+ }
+ case FPGA_AN511:
+ {
+ /* The overflow IRQs for all UARTs are ORed together.
+ * Tx and Rx IRQs for each UART are ORed together.
+ */
+ Object *orgate;
+ DeviceState *orgate_dev;
+ int i;
+
+ orgate = object_new(TYPE_OR_IRQ);
+ object_property_set_int(orgate, 10, "num-lines", &error_fatal);
+ object_property_set_bool(orgate, true, "realized", &error_fatal);
+ orgate_dev = DEVICE(orgate);
+ qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
+
+ for (i = 0; i < 5; i++) {
+ /* system irq numbers for the combined tx/rx for each UART */
+ static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
+ static const hwaddr uartbase[] = {0x40004000, 0x40005000,
+ 0x4002c000, 0x4002d000,
+ 0x4002e000};
+ Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
+ Object *txrx_orgate;
+ DeviceState *txrx_orgate_dev;
+
+ txrx_orgate = object_new(TYPE_OR_IRQ);
+ object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
+ object_property_set_bool(txrx_orgate, true, "realized",
+ &error_fatal);
+ txrx_orgate_dev = DEVICE(txrx_orgate);
+ qdev_connect_gpio_out(txrx_orgate_dev, 0,
+ qdev_get_gpio_in(armv7m,
uart_txrx_irqno[i]));
+ cmsdk_apb_uart_create(uartbase[i],
+ qdev_get_gpio_in(txrx_orgate_dev, 0),
+ qdev_get_gpio_in(txrx_orgate_dev, 1),
+ qdev_get_gpio_in(orgate_dev, 0),
+ qdev_get_gpio_in(orgate_dev, 1),
+ NULL,
+ uartchr, SYSCLK_FRQ);
+ }
+ break;
+ }
+ default:
+ g_assert_not_reached();
+ }
+
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c
index ab34729..1ad1e14 100644
--- a/hw/char/cmsdk-apb-uart.c
+++ b/hw/char/cmsdk-apb-uart.c
@@ -339,7 +339,7 @@ static void cmsdk_apb_uart_realize(DeviceState *dev, Error
**errp)
* an event handler to deal with CHR_EVENT_BREAK.
*/
qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
- NULL, s, NULL, true);
+ NULL, NULL, s, NULL, true);
}
static int cmsdk_apb_uart_post_load(void *opaque, int version_id)
--
2.7.4
- [Qemu-devel] [PULL 00/18] target-arm queue, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 16/18] hw/arm/mps2: Add SCC, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 17/18] hw/arm/mps2: Add ethernet, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 14/18] hw/arm/mps2: Add timers, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 18/18] MAINTAINERS: Add entries for MPS2 board, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 12/18] hw/arm/mps2: Add UARTs,
Peter Maydell <=
- [Qemu-devel] [PULL 06/18] target/arm/translate.h: expand comment on DISAS_EXIT, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 15/18] hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 13/18] hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 08/18] target/arm: use gen_goto_tb for ISB handling, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 07/18] target/arm/translate: ensure gen_goto_tb sets exit flags, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 10/18] hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 04/18] include/exec/exec-all: document common exit conditions, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 05/18] target/arm/translate: make DISAS_UPDATE match declared semantics, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 03/18] target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions, Peter Maydell, 2017/07/17
- [Qemu-devel] [PULL 01/18] qdev-properties.h: Explicitly set the default value for arraylen properties, Peter Maydell, 2017/07/17