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[Qemu-devel] [PATCH v3 17/30] target/sh4: Simplify 64-bit fp reg-reg mov
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 17/30] target/sh4: Simplify 64-bit fp reg-reg move |
Date: |
Tue, 18 Jul 2017 10:02:42 -1000 |
We do not need to form full 64-bit quantities in order to perform
the move. This reduces code expansion on 64-bit hosts.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/sh4/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index bda6fa7..1164f73 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -987,10 +987,10 @@ static void _decode_opc(DisasContext * ctx)
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(ctx, fp, XHACK(B7_4));
- gen_store_fpr64(ctx, fp, XHACK(B11_8));
- tcg_temp_free_i64(fp);
+ int xsrc = XHACK(B7_4);
+ int xdst = XHACK(B11_8);
+ tcg_gen_mov_i32(FREG(xdst), FREG(xsrc));
+ tcg_gen_mov_i32(FREG(xdst + 1), FREG(xsrc + 1));
} else {
tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
}
--
2.9.4
- [Qemu-devel] [PATCH v3 05/30] target/sh4: Adjust TB_FLAG_PENDING_MOVCA, (continued)
- [Qemu-devel] [PATCH v3 05/30] target/sh4: Adjust TB_FLAG_PENDING_MOVCA, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 06/30] target/sh4: Handle user-space atomics, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 07/30] target/sh4: Recognize common gUSA sequences, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 08/30] linux-user/sh4: Notice gUSA regions during signal delivery, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 09/30] linux-user/sh4: Clean env->flags on signal boundaries, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 10/30] target/sh4: Hoist register bank selection, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 12/30] target/sh4: Pass DisasContext to fpr64 routines, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 11/30] target/sh4: Unify cpu_fregs into FREG, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 14/30] target/sh4: Eliminate unused XREG macro, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 16/30] target/sh4: Load/store Dr as 64-bit quantities, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 17/30] target/sh4: Simplify 64-bit fp reg-reg move,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 18/30] target/sh4: Unify code for CHECK_NOT_DELAY_SLOT, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 15/30] target/sh4: Merge DREG into fpr64 routines, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 19/30] target/sh4: Unify code for CHECK_PRIVILEGED, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 20/30] target/sh4: Unify code for CHECK_FPU_ENABLED, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 21/30] target/sh4: Tidy misc illegal insn checks, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 22/30] target/sh4: Introduce CHECK_FPSCR_PR_*, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 24/30] target/sh4: Implement fpchg, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 23/30] target/sh4: Introduce CHECK_SH4A, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 25/30] target/sh4: Add missing FPSCR.PR == 0 checks, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 26/30] target/sh4: Implement fsrra, Richard Henderson, 2017/07/18