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[Qemu-devel] [PULL 10/14] target/sparc: optimize various functions using
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 10/14] target/sparc: optimize various functions using extract op |
Date: |
Tue, 18 Jul 2017 18:57:18 -1000 |
From: Philippe Mathieu-Daudé <address@hidden>
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/sparc/translate.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index aa6734d..67a83b7 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -380,29 +380,25 @@ static inline void gen_goto_tb(DisasContext *s, int
tb_num,
static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
}
static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
}
static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
}
static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
}
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv
src2)
// env->y = (b2 << 31) | (env->y >> 1);
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31);
- tcg_gen_shri_tl(t0, cpu_y, 1);
- tcg_gen_andi_tl(t0, t0, 0x7fffffff);
+ tcg_gen_extract_tl(t0, cpu_y, 1, 31);
tcg_gen_or_tl(t0, t0, r_temp);
tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
--
2.9.4
- [Qemu-devel] [PULL 00/14] tcg-next patch queue, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 02/14] util/cacheinfo: Add missing include for ppc linux, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 01/14] tcg/mips: reserve a register for the guest_base., Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 03/14] tcg: Expand glue macros before stringifying helper names, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 04/14] coccinelle: ignore ASTs pre-parsed cached C files, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 05/14] coccinelle: add a script to optimize tcg op using tcg_gen_extract(), Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 06/14] target/arm: Optimize aarch64 rev16, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 07/14] target/arm: optimize aarch32 rev16, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 08/14] target/m68k: optimize bcd_flags() using extract op, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 09/14] target/ppc: optimize various functions using extract op, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 10/14] target/sparc: optimize various functions using extract op,
Richard Henderson <=
- [Qemu-devel] [PULL 11/14] target/sparc: optimize gen_op_mulscc() using deposit op, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 12/14] target/alpha: optimize gen_cvtlq() using deposit op, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 13/14] tcg/tci: enable bswap16_i64, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL 14/14] tcg: Pass generic CPUState to gen_intermediate_code(), Richard Henderson, 2017/07/19
- Re: [Qemu-devel] [PULL 00/14] tcg-next patch queue, no-reply, 2017/07/19
- Re: [Qemu-devel] [PULL 00/14] tcg-next patch queue, Peter Maydell, 2017/07/19