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[Qemu-devel] [PULL v2 01/14] tcg/mips: reserve a register for the guest_
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL v2 01/14] tcg/mips: reserve a register for the guest_base. |
Date: |
Wed, 19 Jul 2017 13:34:42 -1000 |
From: Jiang Biao <address@hidden>
Reserve a register for the guest_base using ppc code for reference.
By doing so, we do not have to recompute it for every memory load.
Signed-off-by: Jiang Biao <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
---
tcg/mips/tcg-target.inc.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 85756b81d5..1a8169f5fc 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -85,6 +85,10 @@ static const char * const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_TMP2 TCG_REG_T8
#define TCG_TMP3 TCG_REG_T7
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG TCG_REG_S1
+#endif
+
/* check if we really need so many registers :P */
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers. */
@@ -1547,8 +1551,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
@@ -1652,8 +1655,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
@@ -2452,6 +2454,13 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
+#ifndef CONFIG_SOFTMMU
+ if (guest_base) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
/* delay slot */
--
2.13.3
- [Qemu-devel] [PULL v2 00/14] tcg-next patch queue, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 02/14] util/cacheinfo: Add missing include for ppc linux, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 01/14] tcg/mips: reserve a register for the guest_base.,
Richard Henderson <=
- [Qemu-devel] [PULL v2 03/14] tcg: Expand glue macros before stringifying helper names, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 04/14] coccinelle: ignore ASTs pre-parsed cached C files, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 05/14] coccinelle: add a script to optimize tcg op using tcg_gen_extract(), Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 06/14] target/arm: Optimize aarch64 rev16, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 07/14] target/arm: optimize aarch32 rev16, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 08/14] target/m68k: optimize bcd_flags() using extract op, Richard Henderson, 2017/07/19
- [Qemu-devel] [PULL v2 09/14] target/ppc: optimize various functions using extract op, Richard Henderson, 2017/07/19