Re: [Qemu-devel] [PATCH 14/14] target/mips: Enable CP0_EBase.WG on MIPS64 CPUs

[Yongbok Kim]

On 18/07/2017 12:55, James Hogan wrote:
> Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic
> CPUs. This allows 64-bit guests to run KVM itself, which uses
> CP0_EBase.WG to point CP0_EBase at XKPhys.
> 
> Signed-off-by: James Hogan <address@hidden>
> Cc: Yongbok Kim <address@hidden>
> Cc: Aurelien Jarno <address@hidden>
> ---
> Changes in v2:
> - New patch.
> ---
>  target/mips/translate_init.c | 2 ++
>  1 file changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c
> index 741b39023744..255d25bacd03 100644
> --- a/target/mips/translate_init.c
> +++ b/target/mips/translate_init.c
> @@ -640,6 +640,7 @@ static const mips_def_t mips_defs[] =
>          .SYNCI_Step = 32,
>          .CCRes = 2,
>          .CP0_Status_rw_bitmask = 0x36FBFFFF,
> +        .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
>          .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
>                      (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
>                      (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
> @@ -723,6 +724,7 @@ static const mips_def_t mips_defs[] =
>          .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
>                           (1U << CP0PG_RIE),
>          .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
> +        .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
>          .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) 
> |
>                      (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
>                      (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
> 

Reviewed-by: Yongbok Kim <address@hidden>

Regards,
Yongbok