[Qemu-devel] [RFC PATCH for 2.11 13/23] target/arm/translate-a64.c: add FP16 FADD to AdvSIMD 3 Same

[Alex Bennée]

Signed-off-by: Alex Bennée <address@hidden>
---
 target/arm/helper-a64.h    | 1 +
 target/arm/translate-a64.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 48b400ca8e..f4992e7b36 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -47,3 +47,4 @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, 
env, i64, i64, i64)
 
 /* helper_advsimd.c */
 DEF_HELPER_3(advsimd_acgt_f16, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_addh, f32, f32, f32, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 06da8408f6..f6aca395bd 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9764,6 +9764,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext 
*s, uint32_t insn)
         read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
 
         switch (fpopcode) {
+        case 0x2: /* FADD */
+            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x35: /* FACGT */
             gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
-- 
2.13.0