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[Qemu-devel] [PULL 3/4] mps2: Correctly set parent bus for SCC device
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 3/4] mps2: Correctly set parent bus for SCC device |
Date: |
Mon, 24 Jul 2017 18:06:17 +0100 |
A cut-and-paste error meant that instead of setting the
qdev parent bus for the SCC device we were setting it
twice for the ARMv7M container device. Fix this bug.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/arm/mps2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index f727b43..abb0ab6 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -303,7 +303,7 @@ static void mps2_common_init(MachineState *machine)
object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC);
sccdev = DEVICE(&mms->scc);
- qdev_set_parent_bus(armv7m, sysbus_get_default());
+ qdev_set_parent_bus(sccdev, sysbus_get_default());
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
--
2.7.4
- [Qemu-devel] [PULL 0/4] target-arm queue, Peter Maydell, 2017/07/11
- [Qemu-devel] [PULL 4/4] target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode, Peter Maydell, 2017/07/11
- [Qemu-devel] [PULL 2/4] aspeed: Register all watchdogs, Peter Maydell, 2017/07/11
- [Qemu-devel] [PULL 1/4] hw/misc: Add Exynos4210 Pseudo Random Number Generator, Peter Maydell, 2017/07/11
- [Qemu-devel] [PULL 3/4] ARM: KVM: Enable in-kernel timers with user space gic, Peter Maydell, 2017/07/11
- Re: [Qemu-devel] [PULL 0/4] target-arm queue, Peter Maydell, 2017/07/13