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[Qemu-devel] [PULL 1/8] target-mips: Don't stop on [d]mtc0 DESAVE/KScrat
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PULL 1/8] target-mips: Don't stop on [d]mtc0 DESAVE/KScratch |
Date: |
Thu, 3 Aug 2017 15:45:08 +0100 |
From: James Hogan <address@hidden>
Writing to the MIPS DESAVE register (and now the KScratch registers)
will stop translation, supposedly due to risk of execution mode
switches. However these registers are basically RW scratch registers
with no side effects so there is no risk of them triggering execution
mode changes.
Drop the bstate = BS_STOP for these registers for both mtc0 and dmtc0.
Fixes: 7a387fffce50 ("Add MIPS32R2 instructions, and generally straighten out
the instruction decoding. This is also the first percent towards MIPS64
support.")
Signed-off-by: James Hogan <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Yongbok Kim <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/translate.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 51626ae..0bca700 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6386,8 +6386,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
default:
goto cp0_unimplemented;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
default:
goto cp0_unimplemented;
@@ -7714,8 +7712,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
default:
goto cp0_unimplemented;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
default:
goto cp0_unimplemented;
--
2.7.4
- [Qemu-devel] [PULL 0/8] target-mips queue, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 2/8] mips/malta: leave space for the bootmap after the initrd, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 1/8] target-mips: Don't stop on [d]mtc0 DESAVE/KScratch,
Yongbok Kim <=
- [Qemu-devel] [PULL 7/8] target/mips: Drop redundant gen_io_start/stop(), Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 5/8] target-mips: apply CP0.PageMask before writing into TLB entry, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 4/8] mips: Add KVM T&E segment support for TCG, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 3/8] mips: Improve segment defs for KVM T&E guests, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 8/8] target/mips: Fix RDHWR CC with icount, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 6/8] target/mips: Use BS_EXCP where interrupts are expected, Yongbok Kim, 2017/08/03
- Re: [Qemu-devel] [PULL 0/8] target-mips queue, Peter Maydell, 2017/08/04