[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-executi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index() |
Date: |
Thu, 21 Sep 2017 17:41:24 +0100 |
Now that we have a banked FAULTMASK register and banked exceptions,
we can implement the correct check in cpu_mmu_index() for whether
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
handlers which have requested a negative execution priority to run
with the MPU disabled. In v8M the test has to check this for the
current security state and so takes account of banking.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 21 ++++++++++++++++-----
hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++
2 files changed, 45 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b67c29b..c21c592 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1498,6 +1498,21 @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
* (v8M ARM ARM I_PKLD.)
*/
int armv7m_nvic_raw_execution_priority(void *opaque);
+/**
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
+ * priority is negative for the specified security state.
+ * @opaque: the NVIC
+ * @secure: the security state to test
+ * This corresponds to the pseudocode IsReqExecPriNeg().
+ */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
+#else
+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+{
+ return false;
+}
+#endif
/* Interface for defining coprocessor registers.
* Registers are defined in tables of arm_cp_reginfo structs
@@ -2283,11 +2298,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool
ifetch)
if (arm_feature(env, ARM_FEATURE_M)) {
ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
- /* Execution priority is negative if FAULTMASK is set or
- * we're in a HardFault or NMI handler.
- */
- if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
- || env->v7m.faultmask[env->v7m.secure]) {
+ if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
mmu_idx = ARMMMUIdx_MNegPri;
}
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 1f9e1aa..1aa925b 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -368,6 +368,35 @@ static inline int nvic_exec_prio(NVICState *s)
return MIN(running, s->exception_prio);
}
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+{
+ /* Return true if the requested execution priority is negative
+ * for the specified security state, ie that security state
+ * has an active NMI or HardFault or has set its FAULTMASK.
+ * Note that this is not the same as whether the execution
+ * priority is actually negative (for instance AIRCR.PRIS may
+ * mean we don't allow FAULTMASK_NS to actually make the execution
+ * priority negative). Compare pseudocode IsReqExcPriNeg().
+ */
+ NVICState *s = opaque;
+
+ if (s->cpu->env.v7m.faultmask[secure]) {
+ return true;
+ }
+
+ if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
+ s->vectors[ARMV7M_EXCP_HARD].active) {
+ return true;
+ }
+
+ if (s->vectors[ARMV7M_EXCP_NMI].active &&
+ exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
+ return true;
+ }
+
+ return false;
+}
+
bool armv7m_nvic_can_take_pending_exception(void *opaque)
{
NVICState *s = opaque;
--
2.7.4
- [Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, (continued)
- [Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 05/31] xilinx_axienet: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers, Peter Maydell, 2017/09/07
- Re: [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 01/31] target/arm: Implement MSR/MRS access to NS banked registers, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 12/31] nvic: In escalation to HardFault, support HF not being priority -1, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index(),
Peter Maydell <=
- [Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 25/31] hw/i2c/omap_i2c.c: Don't use old_mmio, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions, Peter Maydell, 2017/09/21