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[Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions |
Date: |
Thu, 21 Sep 2017 17:41:21 +0100 |
In v7M, the fixed-priority exceptions are:
Reset: -3
NMI: -2
HardFault: -1
In v8M, this changes because Secure HardFault may need
to be prioritised above NMI:
Reset: -4
Secure HardFault if AIRCR.BFHFNMINS == 1: -3
NMI: -2
Secure HardFault if AIRCR.BFHFNMINS == 0: -1
NonSecure HardFault: -1
Make these changes, including support for changing the
priority of Secure HardFault as AIRCR.BFHFNMINS changes.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 1a8ce01..0c1d591 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -937,6 +937,12 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
(R_V7M_AIRCR_SYSRESETREQS_MASK |
R_V7M_AIRCR_BFHFNMINS_MASK |
R_V7M_AIRCR_PRIS_MASK);
+ /* BFHFNMINS changes the priority of Secure HardFault */
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
+ } else {
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+ }
}
nvic_irq_update(s);
}
@@ -1452,9 +1458,12 @@ static int nvic_post_load(void *opaque, int version_id)
{
NVICState *s = opaque;
unsigned i;
+ int resetprio;
/* Check for out of range priority settings */
- if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
+
+ if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
return 1;
@@ -1497,7 +1506,12 @@ static int nvic_security_post_load(void *opaque, int
version_id)
int i;
/* Check for out of range priority settings */
- if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
+ && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
+ /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
+ * if the CPU state has been migrated yet; a mismatch won't
+ * cause the emulation to blow up, though.
+ */
return 1;
}
for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
@@ -1548,6 +1562,7 @@ static Property props_nvic[] = {
static void armv7m_nvic_reset(DeviceState *dev)
{
+ int resetprio;
NVICState *s = NVIC(dev);
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
@@ -1560,7 +1575,8 @@ static void armv7m_nvic_reset(DeviceState *dev)
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
- s->vectors[ARMV7M_EXCP_RESET].prio = -3;
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
+ s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
--
2.7.4
- [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature, (continued)
- [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers, Peter Maydell, 2017/09/07
- Re: [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 01/31] target/arm: Implement MSR/MRS access to NS banked registers, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 12/31] nvic: In escalation to HardFault, support HF not being priority -1, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions,
Peter Maydell <=
- [Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 25/31] hw/i2c/omap_i2c.c: Don't use old_mmio, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 21/31] hw/arm/palm.c: Don't use old_mmio for static_ops, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 04/31] nvic: Add cached vectpending_prio state, Peter Maydell, 2017/09/21