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[Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked except
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions |
Date: |
Thu, 21 Sep 2017 17:41:14 +0100 |
Update the code in nvic_rettobase() so that it checks the
sec_vectors[] array as well as the vectors[] array if needed.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index d745f38..0df5eaf 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -84,9 +84,12 @@ static int nvic_pending_prio(NVICState *s)
static bool nvic_rettobase(NVICState *s)
{
int irq, nhand = 0;
+ bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
- if (s->vectors[irq].active) {
+ if (s->vectors[irq].active ||
+ (check_sec && irq < NVIC_INTERNAL_VECTORS &&
+ s->sec_vectors[irq].active)) {
nhand++;
if (nhand == 2) {
return 0;
--
2.7.4
- [Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index(), (continued)
- [Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 25/31] hw/i2c/omap_i2c.c: Don't use old_mmio, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions,
Peter Maydell <=
- [Qemu-devel] [PULL 21/31] hw/arm/palm.c: Don't use old_mmio for static_ops, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 04/31] nvic: Add cached vectpending_prio state, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 26/31] hw/arm/omap2.c: Don't use old_mmio, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 24/31] hw/timer/omap_gptimer: Don't use old_mmio, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 07/31] nvic: Implement NVIC_ITNS<n> registers, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 18/31] nvic: Make SHCSR banked for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 29/31] msf2: Add Smartfusion2 SPI controller, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 19/31] nvic: Support banked exceptions in acknowledge and complete, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 23/31] hw/timer/omap_synctimer.c: Don't use old_mmio, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 28/31] msf2: Microsemi Smartfusion2 System Register block, Peter Maydell, 2017/09/21