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[Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns


From: Richard Henderson
Subject: [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns
Date: Wed, 4 Oct 2017 14:43:13 -0400

This patch set depends on v3 of native-vector-registers;
for ease of review the whole tree is at

  git://github.com/rth7680/qemu.git tgt-arm-cplx

I have successfully tested all insns for AArch64 via RISU.
I have successfully tested everything but VCMLA for AArch32.

The insn that doesn't match up is

  fef3c848  vcmla.f32  q14, <illegal reg q1.5>, d8[0], #270

for which FoundationModel is *not* signalling illegal insn.
I'm not really sure what it is doing -- perhaps treating the
insn as a coprocessor 8 nop?  I'll have to investigate further.

In the meantime, it's surely time for a round 1 review.


r~


Richard Henderson (12):
  HACK: use objdump disas
  target/arm: Add ARM_FEATURE_V8_1_SIMD
  target/arm: Decode aa64 armv8.1 scalar three same extra
  target/arm: Decode aa64 armv8.1 three same extra
  target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
  target/arm: Decode aa32 armv8.1 three same
  target/arm: Decode aa32 armv8.1 two reg and a scalar
  target/arm: Add ARM_FEATURE_V8_FCMA
  target/arm: Decode aa64 armv8.3 fcadd
  target/arm: Decode aa64 armv8.3 fcmla
  target/arm: Decode aa32 armv8.3 3-same
  target/arm: Decode aa32 armv8.3 2-reg-index

 target/arm/cpu.h            |   2 +
 target/arm/helper.h         |  26 ++++
 disas.c                     |   2 +-
 linux-user/elfload.c        |  10 ++
 target/arm/advsimd_helper.c | 331 +++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.c            |   2 +
 target/arm/cpu64.c          |   2 +
 target/arm/translate-a64.c  | 350 +++++++++++++++++++++++++++++++++++++++-----
 target/arm/translate.c      | 241 +++++++++++++++++++++++++++---
 target/arm/Makefile.objs    |   2 +-
 10 files changed, 912 insertions(+), 56 deletions(-)
 create mode 100644 target/arm/advsimd_helper.c

-- 
2.13.6




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