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[Qemu-devel] [PATCH v1 05/12] target/arm: Decode aa64 armv8.1 scalar/vec
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v1 05/12] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element |
Date: |
Wed, 4 Oct 2017 14:43:18 -0400 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 46 ++++++++++++++++++++++++++++++++++++++++------
1 file changed, 40 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 0ea47a9dff..b02aad8cd7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10749,12 +10749,23 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
is_long = true;
/* fall through */
case 0xc: /* SQDMULH */
- case 0xd: /* SQRDMULH */
if (u) {
unallocated_encoding(s);
return;
}
break;
+ case 0xd: /* SQRDMULH / SQRDMLAH */
+ if (u && !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
+ case 0xf: /* SQRDMLSH */
+ if (!u || !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
case 0x8: /* MUL */
if (u || is_scalar) {
unallocated_encoding(s);
@@ -10941,13 +10952,36 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
tcg_op, tcg_idx);
}
break;
- case 0xd: /* SQRDMULH */
+ case 0xd: /* SQRDMULH / SQRDMLAH */
+ if (u) { /* SQRDMLAH */
+ read_vec_element_i32(s, tcg_res, rd, pass,
+ is_scalar ? size : MO_32);
+ if (size == 1) {
+ gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ } else {
+ gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ }
+ } else { /* SQRDMULH */
+ if (size == 1) {
+ gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx);
+ } else {
+ gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx);
+ }
+ }
+ break;
+ case 0xf: /* SQRDMLSH */
+ read_vec_element_i32(s, tcg_res, rd, pass,
+ is_scalar ? size : MO_32);
if (size == 1) {
- gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
- tcg_op, tcg_idx);
+ gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
} else {
- gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
- tcg_op, tcg_idx);
+ gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
}
break;
default:
--
2.13.6
- [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 01/12] HACK: use objdump disas, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 03/12] target/arm: Decode aa64 armv8.1 scalar three same extra, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 05/12] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element,
Richard Henderson <=
- [Qemu-devel] [PATCH v1 04/12] target/arm: Decode aa64 armv8.1 three same extra, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 06/12] target/arm: Decode aa32 armv8.1 three same, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 07/12] target/arm: Decode aa32 armv8.1 two reg and a scalar, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 09/12] target/arm: Decode aa64 armv8.3 fcadd, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 10/12] target/arm: Decode aa64 armv8.3 fcmla, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 08/12] target/arm: Add ARM_FEATURE_V8_FCMA, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 11/12] target/arm: Decode aa32 armv8.3 3-same, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 12/12] target/arm: Decode aa32 armv8.3 2-reg-index, Richard Henderson, 2017/10/04
- Re: [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04
- Re: [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04