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[Qemu-devel] [PULL 19/20] target/arm: Factor out "get mmuidx for specifi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/20] target/arm: Factor out "get mmuidx for specified security state" |
Date: |
Fri, 6 Oct 2017 16:59:44 +0100 |
For the SG instruction and secure function return we are going
to want to do memory accesses using the MMU index of the CPU
in secure state, even though the CPU is currently in non-secure
state. Write arm_v7m_mmu_idx_for_secstate() to do this job,
and use it in cpu_mmu_index().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 32 +++++++++++++++++++++-----------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 70c1f85..89d49cd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2329,23 +2329,33 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
}
+/* Return the MMU index for a v7M CPU in the specified security state */
+static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
+ bool secstate)
+{
+ int el = arm_current_el(env);
+ ARMMMUIdx mmu_idx;
+
+ if (el == 0) {
+ mmu_idx = secstate ? ARMMMUIdx_MSUser : ARMMMUIdx_MUser;
+ } else {
+ mmu_idx = secstate ? ARMMMUIdx_MSPriv : ARMMMUIdx_MPriv;
+ }
+
+ if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
+ mmu_idx = secstate ? ARMMMUIdx_MSNegPri : ARMMMUIdx_MNegPri;
+ }
+
+ return mmu_idx;
+}
+
/* Determine the current mmu_idx to use for normal loads/stores */
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
int el = arm_current_el(env);
if (arm_feature(env, ARM_FEATURE_M)) {
- ARMMMUIdx mmu_idx;
-
- if (el == 0) {
- mmu_idx = env->v7m.secure ? ARMMMUIdx_MSUser : ARMMMUIdx_MUser;
- } else {
- mmu_idx = env->v7m.secure ? ARMMMUIdx_MSPriv : ARMMMUIdx_MPriv;
- }
-
- if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
- mmu_idx = env->v7m.secure ? ARMMMUIdx_MSNegPri : ARMMMUIdx_MNegPri;
- }
+ ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
return arm_to_core_mmu_idx(mmu_idx);
}
--
2.7.4
- [Qemu-devel] [PULL 15/20] target/arm: Add v8M support to exception entry code, (continued)
- [Qemu-devel] [PULL 15/20] target/arm: Add v8M support to exception entry code, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 12/20] target/arm: Add new-in-v8M SFSR and SFAR, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 10/20] target/arm: Warn about restoring to unaligned stack, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 11/20] target/arm: Don't warn about exception return with PC low bit set for v8M, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 08/20] target/arm: Restore SPSEL to correct CONTROL register on exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 03/20] hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = false, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 04/20] nvic: Clear the vector arrays and prigroup on reset, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 02/20] hw/sd: fix out-of-bounds check for multi block reads, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 07/20] target/arm: Restore security state on exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 19/20] target/arm: Factor out "get mmuidx for specified security state",
Peter Maydell <=
- [Qemu-devel] [PULL 17/20] target/arm: Implement security attribute lookups for memory accesses, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 01/20] arm: Fix SMC reporting to EL2 when QEMU provides PSCI, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 05/20] target/arm: Don't switch to target stack early in v7M exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 06/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode, Peter Maydell, 2017/10/06
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2017/10/06