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[Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN |
Date: |
Fri, 13 Oct 2017 17:24:13 +0100 |
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée <address@hidden>
---
fpu/softfloat-specialize.h | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index de2c5d5702..c8282b8bf7 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -685,6 +685,49 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
}
#endif
+/*----------------------------------------------------------------------------
+| Takes two half-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status)
+{
+ flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
+ flag aIsLargerSignificand;
+ uint16_t av, bv;
+
+ aIsQuietNaN = float16_is_quiet_nan(a, status);
+ aIsSignalingNaN = float16_is_signaling_nan(a, status);
+ bIsQuietNaN = float16_is_quiet_nan(b, status);
+ bIsSignalingNaN = float16_is_signaling_nan(b, status);
+ av = float16_val(a);
+ bv = float16_val(b);
+
+ if (aIsSignalingNaN | bIsSignalingNaN) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ if (status->default_nan_mode) {
+ return float16_default_nan(status);
+ }
+
+ if ((uint16_t)(av << 1) < (uint16_t)(bv << 1)) {
+ aIsLargerSignificand = 0;
+ } else if ((uint16_t)(bv << 1) < (uint16_t)(av << 1)) {
+ aIsLargerSignificand = 1;
+ } else {
+ aIsLargerSignificand = (av < bv) ? 1 : 0;
+ }
+
+ if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
+ aIsLargerSignificand)) {
+ return float16_maybe_silence_nan(b, status);
+ } else {
+ return float16_maybe_silence_nan(a, status);
+ }
+}
+
/*----------------------------------------------------------------------------
| Takes two single-precision floating-point values `a' and `b', one of which
| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
--
2.14.1
- Re: [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter, (continued)
- [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN,
Alex Bennée <=
- [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX, Alex Bennée, 2017/10/13