[Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton

[Alex Bennée]

This is just the decode skeleton which will be filled out by later
patches.

Signed-off-by: Alex Bennée <address@hidden>
---
 target/arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d12106695f..11990daff4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10568,6 +10568,40 @@ static void disas_simd_two_reg_misc(DisasContext *s, 
uint32_t insn)
     }
 }
 
+/* AdvSIMD two reg misc FP16
+ *   31  30  29 28       24  23 22 21       17 16    12 11 10 9    5 4    0
+ * +---+---+---+-----------+---+-------------+--------+-----+------+------+
+ * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 |  Rn  |  Rd  |
+ * +---+---+---+-----------+---+-------------+--------+-----+------+------+
+ *   mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00
+ *   val:  0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800
+ * Half-precision variants of two-reg misc.
+ */
+static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+{
+    int fpop, opcode, a;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    if (!fp_access_check(s)) {
+        return;
+    }
+
+    opcode = extract32(insn, 12, 4);
+    a = extract32(insn, 23, 1);
+    fpop = deposit32(opcode, 5, 1, a);
+
+    switch (fpop) {
+    default:
+        fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
+        g_assert_not_reached();
+    }
+
+}
+
 /* AdvSIMD scalar x indexed element
  *  31 30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
  * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
@@ -11270,6 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
     { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
     { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
     { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
+    { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 },
     { 0x00000000, 0x00000000, NULL }
 };
 
-- 
2.14.1