[Qemu-devel] [Bug 1723984] Re: ID_MMFR0 has an invalid value on aarch64 cpu (A57, A53)

[Peter Maydell]

You shouldn't need to read the MIDR at all.

There are two sensible strategies for software I think:

 (1) trust the architectural statement that v8 implies that the AIFSR
and ADFSR both exist -- AIUI both QEMU and the hardware implementations
that report 0001 in this MMFR0 field do actually implement those
registers, so this is safe.

 (2) read and pay attention to the AuxReg field, by handling 0001 as
"only Auxiliary Control Register is supported, AIFSR and ADFSR are not
supported". This will work fine too -- on implementations that report
0001 you may be not using the AIFSR/ADFSR but that's ok because on those
implementations they only RAZ/WI anyhow so you couldn't do anything
interesting with them anyway.

If your code is genuinely v8 only then (1) is easiest. If you also need
to support ARMv7 then (2) is best, because 0001 is a permitted value in
ID_MMFR0 for an ARMv7 implementation, so you need to handle it
regardless of the A53/A57 behaviour.

Neither approach requires detecting and special casing A53/A57 revisions
via the MIDR.

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https://bugs.launchpad.net/bugs/1723984

Title:
  ID_MMFR0 has an invalid value on aarch64 cpu (A57, A53)

Status in QEMU:
  New

Bug description:
  The ID_MMFR0 register, accessed from aarch64 state as an invalid value:
  - ARM ARM v8 documentation (D7.2 General system control registers) described 
bits AuxReg[23:20] to be
    "In ARMv8-A the only permitted value is 0010"
  - Cortex A53 and Cortex A57 TRM describe the value to be 0x10201105, so 
AuxReg[23:20] is 0010 too
  - in QEMU target/arm/cpu64.c, the relevant value is
    cpu->id_mmfr0 = 0x10101105;

  The 1 should be changed to 2.

  Spotted & Tested on the following qemu revision:

  commit 48ae1f60d8c9a770e6da64407984d84e25253c69
  Merge: 78b62d3 b867eaa
  Author: Peter Maydell <address@hidden>
  Date:   Mon Oct 16 14:28:13 2017 +0100

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