[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v7 30/52] target/m68k: check CF_PARALLEL instead of
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v7 30/52] target/m68k: check CF_PARALLEL instead of parallel_cpus |
Date: |
Fri, 20 Oct 2017 16:20:01 -0700 |
From: "Emilio G. Cota" <address@hidden>
Thereby decoupling the resulting translated code from the current state
of the system.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/m68k/helper.h | 1 +
target/m68k/op_helper.c | 33 ++++++++++++++++++++-------------
target/m68k/translate.c | 12 ++++++++++--
3 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index 475a1f2186..eebe52dae5 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -11,6 +11,7 @@ DEF_HELPER_2(set_sr, void, env, i32)
DEF_HELPER_3(movec, void, env, i32, i32)
DEF_HELPER_4(cas2w, void, env, i32, i32, i32)
DEF_HELPER_4(cas2l, void, env, i32, i32, i32)
+DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32)
#define dh_alias_fp ptr
#define dh_ctype_fp FPReg *
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 7b5126c88d..63089511cb 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -361,6 +361,7 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int regr,
int32_t den)
env->dregs[numr] = quot;
}
+/* We're executing in a serial context -- no need to be atomic. */
void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
{
uint32_t Dc1 = extract32(regs, 9, 3);
@@ -374,17 +375,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs,
uint32_t a1, uint32_t a2)
int16_t l1, l2;
uintptr_t ra = GETPC();
- if (parallel_cpus) {
- /* Tell the main loop we need to serialize this insn. */
- cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
- } else {
- /* We're executing in a serial context -- no need to be atomic. */
- l1 = cpu_lduw_data_ra(env, a1, ra);
- l2 = cpu_lduw_data_ra(env, a2, ra);
- if (l1 == c1 && l2 == c2) {
- cpu_stw_data_ra(env, a1, u1, ra);
- cpu_stw_data_ra(env, a2, u2, ra);
- }
+ l1 = cpu_lduw_data_ra(env, a1, ra);
+ l2 = cpu_lduw_data_ra(env, a2, ra);
+ if (l1 == c1 && l2 == c2) {
+ cpu_stw_data_ra(env, a1, u1, ra);
+ cpu_stw_data_ra(env, a2, u2, ra);
}
if (c1 != l1) {
@@ -399,7 +394,8 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs,
uint32_t a1, uint32_t a2)
env->dregs[Dc2] = deposit32(env->dregs[Dc2], 0, 16, l2);
}
-void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
+static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t
a2,
+ bool parallel)
{
uint32_t Dc1 = extract32(regs, 9, 3);
uint32_t Dc2 = extract32(regs, 6, 3);
@@ -416,7 +412,7 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs,
uint32_t a1, uint32_t a2)
TCGMemOpIdx oi;
#endif
- if (parallel_cpus) {
+ if (parallel) {
/* We're executing in a parallel context -- must be atomic. */
#ifdef CONFIG_ATOMIC64
uint64_t c, u, l;
@@ -470,6 +466,17 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs,
uint32_t a1, uint32_t a2)
env->dregs[Dc2] = l2;
}
+void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
+{
+ do_cas2l(env, regs, a1, a2, false);
+}
+
+void HELPER(cas2l_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1,
+ uint32_t a2)
+{
+ do_cas2l(env, regs, a1, a2, true);
+}
+
struct bf_data {
uint32_t addr;
uint32_t bofs;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index fdc26268d0..d751faed7c 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2312,7 +2312,11 @@ DISAS_INSN(cas2w)
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- gen_helper_cas2w(cpu_env, regs, addr1, addr2);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_exit_atomic(cpu_env);
+ } else {
+ gen_helper_cas2w(cpu_env, regs, addr1, addr2);
+ }
tcg_temp_free(regs);
/* Note that cas2w also assigned to env->cc_op. */
@@ -2358,7 +2362,11 @@ DISAS_INSN(cas2l)
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- gen_helper_cas2l(cpu_env, regs, addr1, addr2);
+ if (tb_cflags(s->tb) & CF_PARALLEL) {
+ gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
+ } else {
+ gen_helper_cas2l(cpu_env, regs, addr1, addr2);
+ }
tcg_temp_free(regs);
/* Note that cas2l also assigned to env->cc_op. */
--
2.13.6
- [Qemu-devel] [PATCH v7 23/52] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK, (continued)
- [Qemu-devel] [PATCH v7 23/52] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 25/52] tcg: Include CF_COUNT_MASK in CF_HASH_MASK, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 19/52] tcg: Remove TCGV_EQUAL*, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 24/52] tcg: Add CPUState cflags_next_tb, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 29/52] target/i386: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 28/52] target/hppa: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 27/52] target/arm: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 30/52] target/m68k: check CF_PARALLEL instead of parallel_cpus,
Richard Henderson <=
- [Qemu-devel] [PATCH v7 26/52] tcg: convert tb->cflags reads to tb_cflags(tb), Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 32/52] target/sh4: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 31/52] target/s390x: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 33/52] target/sparc: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 34/52] tcg: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 35/52] cpu-exec: lookup/generate TB outside exclusive region during step_atomic, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 36/52] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 37/52] tcg: Remove CF_IGNORE_ICOUNT, Richard Henderson, 2017/10/20