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[Qemu-devel] [PATCH v7 34/52] tcg: check CF_PARALLEL instead of parallel
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v7 34/52] tcg: check CF_PARALLEL instead of parallel_cpus |
Date: |
Fri, 20 Oct 2017 16:20:05 -0700 |
From: "Emilio G. Cota" <address@hidden>
Thereby decoupling the resulting translated code from the current state
of the system.
The tb->cflags field is not passed to tcg generation functions. So
we add a field to TCGContext, storing there a copy of tb->cflags.
Most architectures have <= 32 registers, which results in a 4-byte hole
in TCGContext. Use this hole for the new field.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg.h | 1 +
accel/tcg/translate-all.c | 1 +
tcg/tcg-op.c | 10 +++++-----
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 45d0b7c08e..da969eb321 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -614,6 +614,7 @@ struct TCGContext {
uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
TCGRegSet reserved_regs;
+ uint32_t tb_cflags; /* cflags of the current TB */
intptr_t current_frame_offset;
intptr_t frame_start;
intptr_t frame_end;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 91fd6e444b..dcd47cd692 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1296,6 +1296,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb->flags = flags;
tb->cflags = cflags;
tb->trace_vcpu_dstate = *cpu->trace_dstate;
+ tcg_ctx.tb_cflags = cflags;
#ifdef CONFIG_PROFILER
tcg_ctx.tb_count1++; /* includes aborted translations because of
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 9561510d9c..8c7668de60 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -121,7 +121,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2,
TCGArg a3,
void tcg_gen_mb(TCGBar mb_type)
{
- if (parallel_cpus) {
+ if (tcg_ctx.tb_cflags & CF_PARALLEL) {
tcg_gen_op1(INDEX_op_mb, mb_type);
}
}
@@ -2780,7 +2780,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr,
TCGv_i32 cmpv,
{
memop = tcg_canonicalize_memop(memop, 0, 0);
- if (!parallel_cpus) {
+ if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) {
TCGv_i32 t1 = tcg_temp_new_i32();
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -2824,7 +2824,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr,
TCGv_i64 cmpv,
{
memop = tcg_canonicalize_memop(memop, 1, 0);
- if (!parallel_cpus) {
+ if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) {
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -3001,7 +3001,7 @@ static void * const table_##NAME[16] = {
\
void tcg_gen_atomic_##NAME##_i32 \
(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (parallel_cpus) { \
+ if (tcg_ctx.tb_cflags & CF_PARALLEL) { \
do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \
@@ -3011,7 +3011,7 @@ void tcg_gen_atomic_##NAME##_i32
\
void tcg_gen_atomic_##NAME##_i64 \
(TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (parallel_cpus) { \
+ if (tcg_ctx.tb_cflags & CF_PARALLEL) { \
do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \
--
2.13.6
- [Qemu-devel] [PATCH v7 24/52] tcg: Add CPUState cflags_next_tb, (continued)
- [Qemu-devel] [PATCH v7 24/52] tcg: Add CPUState cflags_next_tb, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 29/52] target/i386: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 28/52] target/hppa: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 27/52] target/arm: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 30/52] target/m68k: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 26/52] tcg: convert tb->cflags reads to tb_cflags(tb), Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 32/52] target/sh4: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 31/52] target/s390x: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 33/52] target/sparc: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 34/52] tcg: check CF_PARALLEL instead of parallel_cpus,
Richard Henderson <=
- [Qemu-devel] [PATCH v7 35/52] cpu-exec: lookup/generate TB outside exclusive region during step_atomic, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 36/52] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 37/52] tcg: Remove CF_IGNORE_ICOUNT, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 39/52] exec-all: rename tb_free to tb_remove, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 38/52] translate-all: use a binary search tree to track TBs in TBContext, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 40/52] translate-all: report correct avg host TB size, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 41/52] tcg: take tb_ctx out of TCGContext, Richard Henderson, 2017/10/20
- [Qemu-devel] [PATCH v7 44/52] tcg: introduce **tcg_ctxs to keep track of all TCGContext's, Richard Henderson, 2017/10/20