Re: [Qemu-devel] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled

[Peter Maydell]

On 30 October 2017 at 22:57, Stefano Stabellini <address@hidden> wrote:
> On Mon, 30 Oct 2017, Peter Maydell wrote:
>> What's the specific situation/bug that you're trying to fix with
>> this patch? You don't say in the commit message.
>> We should be able to put in a point fix to deal with whatever it is,
>> but it's hard to suggest what that would be without the detail
>> of what exactly we're getting wrong. (It's the PAR format stuff,
>> right? But which ATS instruction are you using, from which
>> exception level, with which register width, for which stage
>> 1 page table format and stage 1 guest register width?)
>
> Thank you for understanding, I am not really up for heavy refactoring
> in QEMU right now :-)
>
> Yes, I am trying to fix the AT instruction, which is used by Xen for
> address translations. Xen always runs at EL2. do_ats_write takes the
> wrong path because extended_addresses_enabled assumes EL1.
>
> To go more into details, virt_to_maddr translates a Xen virtual address
> into a physical address. Xen implements virt_to_maddr as:
>
>   static inline paddr_t __virt_to_maddr(vaddr_t va)
>   {
>       uint64_t par = va_to_par(va);
>       return (par & PADDR_MASK & PAGE_MASK) | (va & ~PAGE_MASK);
>   }
>
> Where va_to_par is:
>
>   #define ATS1HR          p15,4,c7,c8,0   /* Address Translation Stage 1 Hyp. 
> Read */
>   static inline uint64_t __va_to_par(vaddr_t va)
>   {
>       uint64_t par, tmp;
>       tmp = READ_CP64(PAR);
>       WRITE_CP32(va, ATS1HR);
>       isb(); /* Ensure result is available. */
>       par = READ_CP64(PAR);
>       WRITE_CP64(tmp, PAR);
>       return par;
>   }
>
> This is what breaks Xen 64-bit booting on qemu-system-aarch64.

I'm confused. You say this is 64-bit booting, but the code you quote
here looks like it's doing 32-bit cp15 accesses, not 64-bit mrs/msr
sysreg accesses.

We definitely don't support 32-bit Hyp mode right now.

Could you please answer all of:
>> which ATS instruction are you using, from which
>> exception level, with which register width, for which stage
>> 1 page table format and stage 1 guest register width?)

thanks
-- PMM