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[Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing er
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking |
Date: |
Tue, 31 Oct 2017 13:11:29 +0000 |
From: Eric Auger <address@hidden>
We exposed gpex_set_irq_num() for machines to set the INTx to
GSI routing. However if the machine forgets to call that
function we currently do not check the association was properly
done. Let's initialize gsi values to -1 and if this value is
found in gpex_route_intx_pin_to_irq, set the routing mode as
disabled.
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/pci-host/gpex.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index 4090793..edf305b 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -57,9 +57,14 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque,
int pin)
{
PCIINTxRoute route;
GPEXHost *s = opaque;
+ int gsi = s->irq_num[pin];
- route.mode = PCI_INTX_ENABLED;
- route.irq = s->irq_num[pin];
+ route.irq = gsi;
+ if (gsi < 0) {
+ route.mode = PCI_INTX_DISABLED;
+ } else {
+ route.mode = PCI_INTX_ENABLED;
+ }
return route;
}
@@ -81,6 +86,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->io_ioport);
for (i = 0; i < GPEX_NUM_IRQS; i++) {
sysbus_init_irq(sbd, &s->irq[i]);
+ s->irq_num[i] = -1;
}
pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,
--
2.7.4
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking,
Peter Maydell <=
- [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register, Peter Maydell, 2017/10/31
- [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs, Peter Maydell, 2017/10/31
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2017/10/31