Re: [Qemu-devel] [PATCH v4] arm: implement cache/shareability attribute bits for PAR registers

[Peter Maydell]

On 31 October 2017 at 22:38, Andrew Baumann
<address@hidden> wrote:
> On a successful address translation instruction, PAR is supposed to
> contain cacheability and shareability attributes determined by the
> translation. We previously returned 0 for these bits (in line with the
> general strategy of ignoring caches and memory attributes), but some
> guest OSes may depend on them.
>
> This patch collects the attribute bits in the page-table walk, and
> updates PAR with the correct attributes for all LPAE translations.
> Short descriptor formats still return 0 for these bits, as in the
> prior implementation.
>
> Signed-off-by: Andrew Baumann <address@hidden>
> ---
> v2:
>  * return attrs via out parameter from get_phys_addr, rather than MemTxAttrs
>  * move MAIR lookup/index inline, since it turned out to be simple
>  * implement attributes for stage 2 translations
>  * combine attributes from stages 1 and 2 when required
>
> v3:
>  * implement S2 allocation hints and check for cache-disabled
>  * fix stage 2 shareability bits
>  * fix combined allocation hints (always use stage 1 hints)
>  * remove LOG_UNIMP message
>
> v4:
>  * fix hihint shift buglet in convert_stage2_attrs
>  * remove TODO comment (what was there is complete)
>  * mention relevant pseudocode procedures in comments
>



Applied to target-arm.next, thanks.

-- PMM