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[Qemu-devel] [Bug 1480562] Re: register values in sp804 timer
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [Bug 1480562] Re: register values in sp804 timer |
Date: |
Fri, 03 Nov 2017 16:26:57 -0000 |
** Changed in: qemu
Status: New => Invalid
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https://bugs.launchpad.net/bugs/1480562
Title:
register values in sp804 timer
Status in QEMU:
Invalid
Bug description:
In the arm_timer.c, when first reading the load register, I got 0.
...
case 0: /* TimerLoad */
...
According to the specification at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html,
"The minimum valid value for TimerXLoad is 1". Is the initial value supposed
to be 0xffffffff?
When the 5th and 7th bit in Control Register are set, RIS and MIS remain 0.
But should they be enabled (i.e., 0x1 and 0x1) as both interrupt and timer
module are set.
Thanks.
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