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Re: [Qemu-devel] [PULL 0/9] target-arm queue


From: Peter Maydell
Subject: Re: [Qemu-devel] [PULL 0/9] target-arm queue
Date: Tue, 14 Nov 2017 13:52:05 +0000

On 13 November 2017 at 14:11, Peter Maydell <address@hidden> wrote:
> ARM bugfixes for rc1...
>
>
> The following changes since commit f291910db61b5812e68f1e76afb3ade41d567bea:
>
>   Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-11-09' into 
> staging (2017-11-13 13:13:12 +0000)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20171113
>
> for you to fetch changes up to d25f2a72272b9ffe0d06710d6217d1169bc2cc7d:
>
>   accel/tcg/translate-all: expand cpu_restore_state addr check (2017-11-13 
> 13:55:27 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * translate-a64.c: silence gcc5 warning
>  * highbank: validate register offset before access
>  * MAINTAINERS: Add entries for Smartfusion2
>  * accel/tcg/translate-all: expand cpu_restore_state addr check
>    (so usermode insn aborts don't crash with an assertion failure)
>  * fix TCG initialization of some Arm boards by allowing them
>    to specify min/default number of CPUs to create
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM



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