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[Qemu-devel] [PULL 2/5] nvic: Fix ARMv7M MPU_RBAR reads
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 2/5] nvic: Fix ARMv7M MPU_RBAR reads |
Date: |
Mon, 20 Nov 2017 17:37:21 +0000 |
Fix an incorrect mask expression in the handling of v7M MPU_RBAR
reads that meant that we would always report the ADDR field as zero.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index be46639..5d9c883 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -977,7 +977,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset,
MemTxAttrs attrs)
if (region >= cpu->pmsav7_dregion) {
return 0;
}
- return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
+ return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf);
}
case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
--
2.7.4
- [Qemu-devel] [PULL 0/5] target-arm queue for rc2, Peter Maydell, 2017/11/20
- [Qemu-devel] [PULL 1/5] target/arm: Report GICv3 sysregs present in ID registers if needed, Peter Maydell, 2017/11/20
- [Qemu-devel] [PULL 5/5] hw/arm: Silence xlnx-ep108 deprecation warning during tests, Peter Maydell, 2017/11/20
- [Qemu-devel] [PULL 2/5] nvic: Fix ARMv7M MPU_RBAR reads,
Peter Maydell <=
- [Qemu-devel] [PULL 3/5] arm: check regime, not current state, for ATS write PAR format, Peter Maydell, 2017/11/20
- [Qemu-devel] [PULL 4/5] hw/arm/aspeed: Unlock SCU when running kernel, Peter Maydell, 2017/11/20
- Re: [Qemu-devel] [PULL 0/5] target-arm queue for rc2, Peter Maydell, 2017/11/21