qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] [PATCH for-2.11?] target/arm: Generate UNDEF for 32-bit Thu


From: Peter Maydell
Subject: [Qemu-devel] [PATCH for-2.11?] target/arm: Generate UNDEF for 32-bit Thumb2 insns
Date: Mon, 11 Dec 2017 15:42:44 +0000

The refactoring of commit 296e5a0a6c3935 has a nasty bug:
it accidentally dropped the generation of code to raise
the UNDEF exception when disas_thumb2_insn() returns nonzero.
This means that 32-bit Thumb2 instruction patterns that
ought to UNDEF just act like nops instead. This is likely
to break any number of things, including the kernel's "disable
the FPU and use the UNDEF exception to identify when to turn
it back on again" trick.

Signed-off-by: Peter Maydell <address@hidden>
---
This is the smallest possible fix that will correct the
bug, for possible inclusion in 2.11; for 2.12 we should
fix the asymmetry where disas_thumb() generates its own
exception-raising code but disas_thumb2() wants the caller
to do it. (This asymmetry is why we didn't notice the
problem in code review.)

I'm not sure whether this should go into 2.11 or not --
this time last week it would have been an easy "yes".

---
 target/arm/translate.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4afb0c8..f120932 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -12245,7 +12245,10 @@ static void thumb_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
     if (is_16bit) {
         disas_thumb_insn(dc, insn);
     } else {
-        disas_thumb2_insn(dc, insn);
+        if (disas_thumb2_insn(dc, insn)) {
+            gen_exception_insn(dc, 4, EXCP_UDEF, syn_uncategorized(),
+                               default_exception_el(dc));
+        }
     }
 
     /* Advance the Thumb condexec condition.  */
-- 
2.7.4




reply via email to

[Prev in Thread] Current Thread [Next in Thread]