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[Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at c
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done |
Date: |
Wed, 13 Dec 2017 18:12:09 +0000 |
From: Francisco Iglesias <address@hidden>
Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands.
Also update interrupts after reading out the interrupt status.
Signed-off-by: Francisco Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/xilinx_spips.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index ab54da8..3805d8b 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
uint8_t addr_length;
if (fifo8_is_empty(&s->tx_fifo)) {
- if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
- s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
- }
xilinx_spips_update_ixr(s);
return;
} else if (s->snoop_state == SNOOP_STRIPING) {
@@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
ret = s->regs[addr] & IXR_ALL;
s->regs[addr] = 0;
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+ xilinx_spips_update_ixr(s);
return ret;
case R_INTR_MASK:
mask = IXR_ALL;
--
2.7.4
- [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 05/43] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 06/43] xilinx_spips: Update striping to be big-endian bit order, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 01/43] m25p80: Add support for continuous read out of RDSR and READ_FSR, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done,
Peter Maydell <=
- [Qemu-devel] [PULL 04/43] m25p80: Add support for n25q512a11 and n25q512a13, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 02/43] m25p80: Add support for SST READ ID 0x90/0xAB commands, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 14/43] hw/intc/arm_gicv3_its: Don't call post_load on reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 15/43] hw/intc/arm_gicv3_its: Implement a minimalist reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 20/43] target/arm: Add missing M profile case to regime_is_user(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 08/43] xilinx_spips: Make tx/rx_data_bytes more generic and reusable, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 07/43] xilinx_spips: Add support for RX discard and RX drain, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI, Peter Maydell, 2017/12/13