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[Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERA
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) |
Date: |
Wed, 13 Dec 2017 18:12:01 +0000 |
From: Francisco Iglesias <address@hidden>
Add support for the bank address register access commands (BRRD/BRWR) and
the BULK_ERASE (0x60) command.
Signed-off-by: Francisco Iglesias <address@hidden>
Acked-by: Marcin KrzemiĆski <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/block/m25p80.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 092c0c6..35efdf0 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -331,7 +331,10 @@ typedef enum {
WRDI = 0x4,
RDSR = 0x5,
WREN = 0x6,
+ BRRD = 0x16,
+ BRWR = 0x17,
JEDEC_READ = 0x9f,
+ BULK_ERASE_60 = 0x60,
BULK_ERASE = 0xc7,
READ_FSR = 0x70,
RDCR = 0x15,
@@ -704,6 +707,7 @@ static void complete_collecting_data(Flash *s)
s->write_enable = false;
}
break;
+ case BRWR:
case EXTEND_ADDR_WRITE:
s->ear = s->data[0];
break;
@@ -1050,6 +1054,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
s->state = STATE_READING_DATA;
break;
+ case BULK_ERASE_60:
case BULK_ERASE:
if (s->write_enable) {
DB_PRINT_L(0, "chip erase\n");
@@ -1067,12 +1072,14 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case EX_4BYTE_ADDR:
s->four_bytes_address_mode = false;
break;
+ case BRRD:
case EXTEND_ADDR_READ:
s->data[0] = s->ear;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
+ case BRWR:
case EXTEND_ADDR_WRITE:
if (s->write_enable) {
s->needed_bytes = 1;
--
2.7.4
- [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 05/43] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 06/43] xilinx_spips: Update striping to be big-endian bit order, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 01/43] m25p80: Add support for continuous read out of RDSR and READ_FSR, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 04/43] m25p80: Add support for n25q512a11 and n25q512a13, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60),
Peter Maydell <=
- [Qemu-devel] [PULL 02/43] m25p80: Add support for SST READ ID 0x90/0xAB commands, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 14/43] hw/intc/arm_gicv3_its: Don't call post_load on reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 15/43] hw/intc/arm_gicv3_its: Implement a minimalist reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 20/43] target/arm: Add missing M profile case to regime_is_user(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 08/43] xilinx_spips: Make tx/rx_data_bytes more generic and reusable, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 07/43] xilinx_spips: Add support for RX discard and RX drain, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 17/43] hw/intc/arm_gicv3_its: Implement full reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 18/43] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads, Peter Maydell, 2017/12/13