[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping |
Date: |
Wed, 13 Dec 2017 18:12:07 +0000 |
From: Francisco Iglesias <address@hidden>
Add support for zero pumping according to the transfer size register.
Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/ssi/xilinx_spips.h | 2 ++
hw/ssi/xilinx_spips.c | 47 ++++++++++++++++++++++++++++++++++++-------
2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
index bac90a5..ad2175a 100644
--- a/include/hw/ssi/xilinx_spips.h
+++ b/include/hw/ssi/xilinx_spips.h
@@ -76,6 +76,8 @@ struct XilinxSPIPS {
uint32_t rx_discard;
uint32_t regs[XLNX_SPIPS_R_MAX];
+
+ bool man_start_com;
};
typedef struct {
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 4621dbb..878b17e 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -109,6 +109,7 @@
FIELD(CMND, DUMMY_CYCLES, 2, 6)
#define R_CMND_DMA_EN (1 << 1)
#define R_CMND_PUSH_WAIT (1 << 0)
+#define R_TRANSFER_SIZE (0xc4 / 4)
#define R_LQSPI_STS (0xA4 / 4)
#define LQSPI_STS_WR_RECVD (1 << 1)
@@ -227,6 +228,7 @@ static void xilinx_spips_reset(DeviceState *d)
s->link_state_next_when = 0;
s->snoop_state = SNOOP_CHECKING;
s->cmd_dummies = 0;
+ s->man_start_com = false;
xilinx_spips_update_ixr(s);
xilinx_spips_update_cs_lines(s);
}
@@ -464,6 +466,41 @@ static inline void tx_data_bytes(Fifo8 *fifo, uint32_t
value, int num, bool be)
}
}
+static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
+{
+ if (!s->regs[R_TRANSFER_SIZE]) {
+ return;
+ }
+ if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) {
+ return;
+ }
+ /*
+ * The zero pump must never fill tx fifo such that rx overflow is
+ * possible
+ */
+ while (s->regs[R_TRANSFER_SIZE] &&
+ s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
+ /* endianess just doesn't matter when zero pumping */
+ tx_data_bytes(&s->tx_fifo, 0, 4, false);
+ s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
+ s->regs[R_TRANSFER_SIZE] -= 4;
+ }
+}
+
+static void xilinx_spips_check_flush(XilinxSPIPS *s)
+{
+ if (s->man_start_com ||
+ (!fifo8_is_empty(&s->tx_fifo) &&
+ !(s->regs[R_CONFIG] & MAN_START_EN))) {
+ xilinx_spips_check_zero_pump(s);
+ xilinx_spips_flush_txfifo(s);
+ }
+ if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) {
+ s->man_start_com = false;
+ }
+ xilinx_spips_update_ixr(s);
+}
+
static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max)
{
int i;
@@ -533,7 +570,6 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int mask = ~0;
- int man_start_com = 0;
XilinxSPIPS *s = opaque;
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
@@ -541,8 +577,8 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
switch (addr) {
case R_CONFIG:
mask = ~(R_CONFIG_RSVD | MAN_START_COM);
- if (value & MAN_START_COM) {
- man_start_com = 1;
+ if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) {
+ s->man_start_com = true;
}
break;
case R_INTR_STATUS:
@@ -588,10 +624,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
no_reg_update:
xilinx_spips_update_cs_lines(s);
- if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
- (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN))
{
- xilinx_spips_flush_txfifo(s);
- }
+ xilinx_spips_check_flush(s);
xilinx_spips_update_cs_lines(s);
xilinx_spips_update_ixr(s);
}
--
2.7.4
- [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 05/43] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 06/43] xilinx_spips: Update striping to be big-endian bit order, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 01/43] m25p80: Add support for continuous read out of RDSR and READ_FSR, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 04/43] m25p80: Add support for n25q512a11 and n25q512a13, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 02/43] m25p80: Add support for SST READ ID 0x90/0xAB commands, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping,
Peter Maydell <=
- [Qemu-devel] [PULL 14/43] hw/intc/arm_gicv3_its: Don't call post_load on reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 15/43] hw/intc/arm_gicv3_its: Implement a minimalist reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 20/43] target/arm: Add missing M profile case to regime_is_user(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 08/43] xilinx_spips: Make tx/rx_data_bytes more generic and reusable, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 07/43] xilinx_spips: Add support for RX discard and RX drain, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 17/43] hw/intc/arm_gicv3_its: Implement full reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 18/43] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 12/43] xilinx_spips: Add support for the ZynqMP Generic QSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 13/43] xlnx-zcu102: Add support for the ZynqMP QSPI, Peter Maydell, 2017/12/13