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[Qemu-devel] [PULL 36/43] target/arm: Extend PAR format determination
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 36/43] target/arm: Extend PAR format determination |
Date: |
Wed, 13 Dec 2017 18:12:34 +0000 |
From: "Edgar E. Iglesias" <address@hidden>
Now that do_ats_write() is entirely in control of whether to
generate a 32-bit PAR or a 64-bit PAR, we can make it use the
correct (complicated) condition for doing so.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: Rebased Edgar's patch on top of get_phys_addr() refactoring;
use arm_s1_regime_using_lpae_format() rather than
regime_using_lpae_format() because the latter will assert
if passed ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1;
updated commit message appropriately]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 33 +++++++++++++++++++++++++++++----
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c469e6a..d1395f9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2162,16 +2162,41 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
int prot;
bool ret;
uint64_t par64;
+ bool format64 = false;
MemTxAttrs attrs = {};
ARMMMUFaultInfo fi = {};
ARMCacheAttrs cacheattrs = {};
ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
&prot, &page_size, &fi, &cacheattrs);
- /* TODO: this is not the correct condition to use to decide whether
- * to report a PAR in 64-bit or 32-bit format.
- */
- if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
+
+ if (is_a64(env)) {
+ format64 = true;
+ } else if (arm_feature(env, ARM_FEATURE_LPAE)) {
+ /*
+ * ATS1Cxx:
+ * * TTBCR.EAE determines whether the result is returned using the
+ * 32-bit or the 64-bit PAR format
+ * * Instructions executed in Hyp mode always use the 64bit format
+ *
+ * ATS1S2NSOxx uses the 64bit format if any of the following is true:
+ * * The Non-secure TTBCR.EAE bit is set to 1
+ * * The implementation includes EL2, and the value of HCR.VM is 1
+ *
+ * ATS1Hx always uses the 64bit format (not supported yet).
+ */
+ format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
+
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
+ format64 |= env->cp15.hcr_el2 & HCR_VM;
+ } else {
+ format64 |= arm_current_el(env) == 2;
+ }
+ }
+ }
+
+ if (format64) {
/* Create a 64-bit PAR */
par64 = (1 << 11); /* LPAE bit always set */
if (!ret) {
--
2.7.4
- [Qemu-devel] [PULL 16/43] linux-headers: update to 4.15-rc1, (continued)
- [Qemu-devel] [PULL 16/43] linux-headers: update to 4.15-rc1, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 34/43] target/arm: Ignore fsr from get_phys_addr() in do_ats_write(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 32/43] target/arm: Convert get_phys_addr_pmsav8() to not return FSC values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 35/43] target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 19/43] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 37/43] nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 40/43] MAINTAINERS: replace the unavailable email address, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 41/43] xilinx_spips: Update the QSPI Mod ID reset value, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 42/43] xilinx_spips: Set all of the reset values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 33/43] target/arm: Use ARMMMUFaultInfo in deliver_fault(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 36/43] target/arm: Extend PAR format determination,
Peter Maydell <=
- [Qemu-devel] [PULL 39/43] hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 38/43] nvic: Make systick banked, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 43/43] xilinx_spips: Use memset instead of a for loop to zero registers, Peter Maydell, 2017/12/13
- Re: [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2017/12/14