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[Qemu-devel] [PULL 08/46] x86/cpu: Enable new SSE/AVX/AVX512 cpu feature
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 08/46] x86/cpu: Enable new SSE/AVX/AVX512 cpu features |
Date: |
Wed, 20 Dec 2017 18:14:20 +0100 |
From: Yang Zhong <address@hidden>
Intel IceLake cpu has added new cpu features,AVX512_VBMI2/GFNI/
VAES/VPCLMULQDQ/AVX512_VNNI/AVX512_BITALG. Those new cpu features
need expose to guest VM.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512_VBMI2
CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Yang Zhong <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
target/i386/cpu.c | 6 +++---
target/i386/cpu.h | 6 ++++++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 82603e3..325b52e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -437,9 +437,9 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_7_0_ECX] = {
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
- "ospke", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, "avx512-vpopcntdq", NULL,
+ "ospke", NULL, "avx512vbmi2", NULL,
+ "gfni", "vaes", "vpclmulqdq", "avx512vnni",
+ "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
NULL, NULL, "rdpid", NULL,
NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b086b15..cdbf8b0 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -635,6 +635,12 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_ECX_UMIP (1U << 2)
#define CPUID_7_0_ECX_PKU (1U << 3)
#define CPUID_7_0_ECX_OSPKE (1U << 4)
+#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
+#define CPUID_7_0_ECX_GFNI (1U << 8)
+#define CPUID_7_0_ECX_VAES (1U << 9)
+#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
+#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
+#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of
DW/QW */
#define CPUID_7_0_ECX_LA57 (1U << 16)
#define CPUID_7_0_ECX_RDPID (1U << 22)
--
1.8.3.1
- [Qemu-devel] [PULL 00/46] First batch of misc patches for QEMU 2.12, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 01/46] memfd: fix configure test, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 02/46] qemu-thread: fix races on threads that exit very quickly, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 03/46] qemu-pr-helper: miscellaneous fixes, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 04/46] contrib: add systemd unit files, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 06/46] scsi-block: Add share-rw option, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 05/46] Revert "docker: Enable features explicitly in test-full", Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 07/46] MAITAINERS: List Fam Zheng as reviewer for SCSI patches, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 09/46] hyperv: set partition-wide MSRs only on first vcpu, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 10/46] hyperv: ensure SINTx msrs are reset properly, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 08/46] x86/cpu: Enable new SSE/AVX/AVX512 cpu features,
Paolo Bonzini <=
- [Qemu-devel] [PULL 12/46] cpus: make pause_all_cpus() play with SMP on single threaded TCG, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 13/46] cpu-exec: fix missed CPU kick during interrupt injection, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 11/46] hyperv: make SynIC version msr constant, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 14/46] target/i386: Fix compiler warnings, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 15/46] baum: Truncate braille device size to 84x1, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 18/46] tests/boot-serial-test: Make sure that we check the timeout regularly, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 17/46] target/i386: Fix handling of VEX prefixes, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 19/46] tests/boot-serial-test: Add code to allow to specify our own kernel or bios, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 22/46] hw/moxie/moxiesim: Add support for loading a BIOS on moxiesim, Paolo Bonzini, 2017/12/20
- [Qemu-devel] [PULL 21/46] tests/boot-serial-test: Add tests for microblaze boards, Paolo Bonzini, 2017/12/20