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[Qemu-devel] [PATCH v3 14/42] sdhci: fix CAPAB/MAXCURR registers, both a
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v3 14/42] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only |
Date: |
Fri, 29 Dec 2017 14:49:05 -0300 |
running qtests:
$ make check-qtest-arm
GTESTER check-qtest-arm
SDHC rd_4b @0x44 not implemented
SDHC wr_4b @0x40 <- 0x89abcdef not implemented
SDHC wr_4b @0x44 <- 0x01234567 not implemented
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
include/hw/sd/sdhci.h | 4 ++--
hw/sd/sdhci.c | 23 +++++++++++++++++++----
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index da943a6562..9436375b1e 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -86,9 +86,9 @@ typedef struct SDHCIState {
/* Read-only registers */
/* 0x40 */
- uint32_t capareg; /* Capabilities Register */
+ uint64_t capareg; /* Capabilities Register */
/* 0x48 */
- uint32_t maxcurr; /* Maximum Current Capabilities Register */
+ uint64_t maxcurr; /* Maximum Current Capabilities Register */
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
uint32_t buf_maxsz;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 604ad525f6..ae84af46da 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -904,10 +904,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
unsigned size)
ret = s->acmd12errsts;
break;
case SDHC_CAPAB:
- ret = s->capareg;
+ ret = (uint32_t)s->capareg;
+ break;
+ case SDHC_CAPAB + 4:
+ ret = (uint32_t)(s->capareg >> 32);
break;
case SDHC_MAXCURR:
- ret = s->maxcurr;
+ ret = (uint32_t)s->maxcurr;
+ break;
+ case SDHC_MAXCURR + 4:
+ ret = (uint32_t)(s->maxcurr >> 32);
break;
case SDHC_ADMAERR:
ret = s->admaerr;
@@ -1129,6 +1135,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
}
sdhci_update_irq(s);
break;
+
+ case SDHC_CAPAB:
+ case SDHC_CAPAB + 4:
+ case SDHC_MAXCURR:
+ case SDHC_MAXCURR + 4:
+ qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
+ " <- 0x%08x read-only\n", size, offset, value >> shift);
+ break;
+
default:
qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
"not implemented\n", size, offset, value >> shift);
@@ -1260,9 +1275,9 @@ const VMStateDescription sdhci_vmstate = {
/* Capabilities registers provide information on supported features of this
* specific host controller implementation */
static Property sdhci_properties[] = {
- DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
+ DEFINE_PROP_UINT64("capareg", SDHCIState, capareg,
SDHC_CAPAB_REG_DEFAULT),
- DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
+ DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0),
DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
false),
DEFINE_PROP_END_OF_LIST(),
--
2.15.1
- [Qemu-devel] [PATCH v3 04/42] sdhci: refactor same sysbus/pci properties into a common one, (continued)
- [Qemu-devel] [PATCH v3 04/42] sdhci: refactor same sysbus/pci properties into a common one, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 05/42] sdhci: refactor common sysbus/pci class_init() into sdhci_class_init(), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 06/42] sdhci: refactor common sysbus/pci realize() into sdhci_realizefn(), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 07/42] sdhci: refactor common sysbus/pci unrealize() into sdhci_unrealizefn(), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 08/42] sdhci: use qemu_log_mask(UNIMP) instead of fprintf(), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 09/42] sdhci: convert the DPRINT() calls into trace events, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 10/42] sdhci: add a GPIO for the 'access control' LED, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 11/42] sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h", Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 12/42] sdhci: use FIELD_DP32() macro for the WRITE_PROTECT flag, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 13/42] sdhci: rename the SDHC_CAPAB register, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 14/42] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v3 15/42] sdhci: Implement write method of ACMD12ERRSTS register, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 16/42] sdhci: use deposit64() on admasysaddr, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 17/42] sdhci: add a "dma-memory" property, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 18/42] sdhci: add a spec_version property, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 19/42] sdhci: add basic Spec v1 capabilities, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 20/42] sdhci: add max-block-length capability (Spec v1), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 22/42] sdhci: add DMA and 64-bit capabilities (Spec v2), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 23/42] sdhci: default to Spec v2, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 24/42] sdhci: add a 'dma' shortcut property, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 26/42] sdhci: Fix 64-bit ADMA2, Philippe Mathieu-Daudé, 2017/12/29