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[Qemu-devel] [PATCH v5 14/17] target/m68k: add 680x0 "move to SR" instru
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v5 14/17] target/m68k: add 680x0 "move to SR" instruction |
Date: |
Tue, 2 Jan 2018 02:10:29 +0100 |
Some cleanup, and allows SR to be moved from any addressing mode.
Previous code was wrong for coldfire: coldfire also allows to
use addressing mode to set SR/CCR. It only supports Data register
to get SR/CCR (move from)
Signed-off-by: Laurent Vivier <address@hidden>
---
target/m68k/translate.c | 38 ++++++++++++++++++++++----------------
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index cfe9fd34df..1a462064be 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2162,27 +2162,34 @@ static void gen_set_sr_im(DisasContext *s, uint16_t
val, int ccr_only)
tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
} else {
- gen_helper_set_sr(cpu_env, tcg_const_i32(val));
+ TCGv sr = tcg_const_i32(val);
+ gen_helper_set_sr(cpu_env, sr);
+ tcg_temp_free(sr);
}
set_cc_op(s, CC_OP_FLAGS);
}
-static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
- int ccr_only)
+static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
{
- if ((insn & 0x38) == 0) {
- if (ccr_only) {
- gen_helper_set_ccr(cpu_env, DREG(insn, 0));
- } else {
- gen_helper_set_sr(cpu_env, DREG(insn, 0));
- }
- set_cc_op(s, CC_OP_FLAGS);
- } else if ((insn & 0x3f) == 0x3c) {
+ if (ccr_only) {
+ gen_helper_set_ccr(cpu_env, val);
+ } else {
+ gen_helper_set_sr(cpu_env, val);
+ }
+ set_cc_op(s, CC_OP_FLAGS);
+}
+
+static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
+ bool ccr_only)
+{
+ if ((insn & 0x3f) == 0x3c) {
uint16_t val;
val = read_im16(env, s);
gen_set_sr_im(s, val, ccr_only);
} else {
- disas_undef(env, s, insn);
+ TCGv src;
+ SRC_EA(env, src, OS_WORD, 0, NULL);
+ gen_set_sr(s, src, ccr_only);
}
}
@@ -2557,7 +2564,7 @@ DISAS_INSN(neg)
DISAS_INSN(move_to_ccr)
{
- gen_set_sr(env, s, insn, 1);
+ gen_move_to_sr(env, s, insn, true);
}
DISAS_INSN(not)
@@ -4471,7 +4478,7 @@ DISAS_INSN(move_to_sr)
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return;
}
- gen_set_sr(env, s, insn, 0);
+ gen_move_to_sr(env, s, insn, false);
gen_lookup_tb(s);
}
@@ -5618,9 +5625,8 @@ void register_m68k_insns (CPUM68KState *env)
BASE(move_to_ccr, 44c0, ffc0);
INSN(not, 4680, fff8, CF_ISA_A);
INSN(not, 4600, ff00, M68000);
- INSN(undef, 46c0, ffc0, M68000);
#if defined(CONFIG_SOFTMMU)
- INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
+ BASE(move_to_sr, 46c0, ffc0);
#endif
INSN(nbcd, 4800, ffc0, M68000);
INSN(linkl, 4808, fff8, M68000);
--
2.14.3
- [Qemu-devel] [PATCH v5 00/17] target/m68k: supervisor mode (part 1), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 02/17] target/m68k: fix gen_get_ccr(), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 01/17] target-m68k: sync CC_OP before gen_jmp_tb(), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 06/17] target/m68k: manage 680x0 stack frames, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 04/17] target-m68k: use insn_pc to generate instruction fault address, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 14/17] target/m68k: add 680x0 "move to SR" instruction,
Laurent Vivier <=
- [Qemu-devel] [PATCH v5 12/17] target/m68k: implement fsave/frestore, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 17/17] target/m68k: fix m68k_cpu_dump_state(), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 03/17] linux-user, m68k: correctly manage SR in context, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 05/17] target/m68k: add CPU_LOG_INT trace, Laurent Vivier, 2018/01/01