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[Qemu-devel] [PATCH v4 17/17] sdhci: add a "dma-memory" property
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v4 17/17] sdhci: add a "dma-memory" property |
Date: |
Wed, 3 Jan 2018 08:01:26 -0300 |
Add a dma property allowing machine creation to provide the address-space
sdhci dma operates on.
[based on a patch from Alistair Francis <address@hidden>
from qemu/xilinx tag xilinx-v2016.1]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
include/hw/sd/sdhci.h | 2 ++
hw/sd/sdhci.c | 36 +++++++++++++++++++++++-------------
2 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 9436375b1e..2aea20f1d8 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -41,6 +41,8 @@ typedef struct SDHCIState {
/*< public >*/
SDBus sdbus;
MemoryRegion iomem;
+ MemoryRegion *dma_mr;
+ AddressSpace dma_as;
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
QEMUTimer *transfer_timer;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 97129e178e..a5e63dbd56 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -502,7 +502,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
s->blkcnt--;
}
}
- dma_memory_write(&address_space_memory, s->sdmasysad,
+ dma_memory_write(&s->dma_as, s->sdmasysad,
&s->fifo_buffer[begin], s->data_count - begin);
s->sdmasysad += s->data_count - begin;
if (s->data_count == block_size) {
@@ -524,7 +524,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
s->data_count = block_size;
boundary_count -= block_size - begin;
}
- dma_memory_read(&address_space_memory, s->sdmasysad,
+ dma_memory_read(&s->dma_as, s->sdmasysad,
&s->fifo_buffer[begin], s->data_count - begin);
s->sdmasysad += s->data_count - begin;
if (s->data_count == block_size) {
@@ -562,11 +562,9 @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s)
for (n = 0; n < datacnt; n++) {
s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
}
- dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
- datacnt);
+ dma_memory_write(&s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
} else {
- dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
- datacnt);
+ dma_memory_read(&s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
for (n = 0; n < datacnt; n++) {
sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
}
@@ -590,7 +588,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr
*dscr)
hwaddr entry_addr = (hwaddr)s->admasysaddr;
switch (SDHC_DMA_TYPE(s->hostctl)) {
case SDHC_CTRL_ADMA2_32:
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
+ dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)&adma2,
sizeof(adma2));
adma2 = le64_to_cpu(adma2);
/* The spec does not specify endianness of descriptor table.
@@ -602,7 +600,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr
*dscr)
dscr->incr = 8;
break;
case SDHC_CTRL_ADMA1_32:
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
+ dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)&adma1,
sizeof(adma1));
adma1 = le32_to_cpu(adma1);
dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
@@ -615,12 +613,12 @@ static void get_adma_description(SDHCIState *s, ADMADescr
*dscr)
}
break;
case SDHC_CTRL_ADMA2_64:
- dma_memory_read(&address_space_memory, entry_addr,
+ dma_memory_read(&s->dma_as, entry_addr,
(uint8_t *)(&dscr->attr), 1);
- dma_memory_read(&address_space_memory, entry_addr + 2,
+ dma_memory_read(&s->dma_as, entry_addr + 2,
(uint8_t *)(&dscr->length), 2);
dscr->length = le16_to_cpu(dscr->length);
- dma_memory_read(&address_space_memory, entry_addr + 4,
+ dma_memory_read(&s->dma_as, entry_addr + 4,
(uint8_t *)(&dscr->addr), 8);
dscr->attr = le64_to_cpu(dscr->attr);
dscr->attr &= 0xfffffff8;
@@ -679,7 +677,7 @@ static void sdhci_do_adma(SDHCIState *s)
s->data_count = block_size;
length -= block_size - begin;
}
- dma_memory_write(&address_space_memory, dscr.addr,
+ dma_memory_write(&s->dma_as, dscr.addr,
&s->fifo_buffer[begin],
s->data_count - begin);
dscr.addr += s->data_count - begin;
@@ -703,7 +701,7 @@ static void sdhci_do_adma(SDHCIState *s)
s->data_count = block_size;
length -= block_size - begin;
}
- dma_memory_read(&address_space_memory, dscr.addr,
+ dma_memory_read(&s->dma_as, dscr.addr,
&s->fifo_buffer[begin],
s->data_count - begin);
dscr.addr += s->data_count - begin;
@@ -1198,10 +1196,20 @@ static void sdhci_realizefn(SDHCIState *s, Error **errp)
memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
SDHC_REGISTERS_MAP_SIZE);
+
+ /* use system_memory() if property "dma-memory" not set */
+ address_space_init(&s->dma_as,
+ s->dma_mr ? s->dma_mr : get_system_memory(),
+ "sdhci-dma");
}
static void sdhci_unrealizefn(SDHCIState *s, Error **errp)
{
+ if (s->dma_mr) {
+ address_space_destroy(&s->dma_as);
+ object_unparent(OBJECT(&s->dma_mr));
+ }
+
g_free(s->fifo_buffer);
/* This function is expected to be called only once for each class:
* - SysBus: via DeviceClass->unrealize(),
@@ -1288,6 +1296,8 @@ static Property sdhci_properties[] = {
DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0),
DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
false),
+ DEFINE_PROP_LINK("dma-memory", SDHCIState, dma_mr,
+ TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
--
2.15.1
- Re: [Qemu-devel] [PATCH v4 06/17] sdhci: refactor common sysbus/pci realize() into sdhci_realizefn(), (continued)
- [Qemu-devel] [PATCH v4 08/17] sdhci: use qemu_log_mask(UNIMP) instead of fprintf(), Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 09/17] sdhci: convert the DPRINT() calls into trace events, Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 10/17] sdhci: add a GPIO for the 'access control' LED, Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 11/17] sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h", Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 12/17] sdhci: use FIELD_DP32() macro for the WRITE_PROTECT flag, Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 13/17] sdhci: rename the SDHC_CAPAB register, Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 14/17] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only, Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 15/17] sdhci: Implement write method of ACMD12ERRSTS register, Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 16/17] sdhci: use deposit64() on admasysaddr, Philippe Mathieu-Daudé, 2018/01/03
- [Qemu-devel] [PATCH v4 17/17] sdhci: add a "dma-memory" property,
Philippe Mathieu-Daudé <=
- Re: [Qemu-devel] [PATCH v4 00/17] SDHCI: housekeeping, no-reply, 2018/01/03